Module Name: src
Committed By: ryo
Date: Wed Aug 24 19:21:41 UTC 2022
Modified Files:
src/sys/dev/ic: dwc_eqos.c dwc_eqos_reg.h
Log Message:
rename EQOS_TDES3_* macro to EQOS_TDES3_{TX,RX}_*, and add more defs.
Avoid confusion because some definitions are different bits with the same name
for TX and RX.
no functional changes.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/dev/ic/dwc_eqos.c
cvs rdiff -u -r1.5 -r1.6 src/sys/dev/ic/dwc_eqos_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_eqos.c
diff -u src/sys/dev/ic/dwc_eqos.c:1.11 src/sys/dev/ic/dwc_eqos.c:1.12
--- src/sys/dev/ic/dwc_eqos.c:1.11 Wed Aug 24 03:03:58 2022
+++ src/sys/dev/ic/dwc_eqos.c Wed Aug 24 19:21:41 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos.c,v 1.11 2022/08/24 03:03:58 ryo Exp $ */
+/* $NetBSD: dwc_eqos.c,v 1.12 2022/08/24 19:21:41 ryo Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -33,7 +33,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.11 2022/08/24 03:03:58 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.12 2022/08/24 19:21:41 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -259,7 +259,7 @@ eqos_setup_txdesc(struct eqos_softc *sc,
tdes3 = 0;
--sc->sc_tx.queued;
} else {
- tdes2 = (flags & EQOS_TDES3_LD) ? EQOS_TDES2_IOC : 0;
+ tdes2 = (flags & EQOS_TDES3_TX_LD) ? EQOS_TDES2_TX_IOC : 0;
tdes3 = flags;
++sc->sc_tx.queued;
}
@@ -315,18 +315,18 @@ eqos_setup_txbuf(struct eqos_softc *sc,
/* stored in same index as loaded map */
sc->sc_tx.buf_map[index].mbuf = m;
- flags = EQOS_TDES3_FD;
+ flags = EQOS_TDES3_TX_FD;
for (cur = index, i = 0; i < nsegs; i++) {
if (i == nsegs - 1)
- flags |= EQOS_TDES3_LD;
+ flags |= EQOS_TDES3_TX_LD;
eqos_setup_txdesc(sc, cur, flags, segs[i].ds_addr,
segs[i].ds_len, m->m_pkthdr.len);
- flags &= ~EQOS_TDES3_FD;
+ flags &= ~EQOS_TDES3_TX_FD;
cur = TX_NEXT(cur);
- flags |= EQOS_TDES3_OWN;
+ flags |= EQOS_TDES3_TX_OWN;
}
/*
@@ -341,7 +341,7 @@ eqos_setup_txbuf(struct eqos_softc *sc,
DPRINTF(EDEB_TXRING, "passing tx desc %u to hardware, cur: %u, "
"next: %u, queued: %u\n",
index, sc->sc_tx.cur, sc->sc_tx.next, sc->sc_tx.queued);
- sc->sc_tx.desc_ring[index].tdes3 |= htole32(EQOS_TDES3_OWN);
+ sc->sc_tx.desc_ring[index].tdes3 |= htole32(EQOS_TDES3_TX_OWN);
return nsegs;
}
@@ -356,8 +356,8 @@ eqos_setup_rxdesc(struct eqos_softc *sc,
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx.desc_map,
DESC_OFF(index), offsetof(struct eqos_dma_desc, tdes3),
BUS_DMASYNC_PREWRITE);
- sc->sc_rx.desc_ring[index].tdes3 =
- htole32(EQOS_TDES3_OWN | EQOS_TDES3_IOC | EQOS_TDES3_BUF1V);
+ sc->sc_rx.desc_ring[index].tdes3 = htole32(EQOS_TDES3_RX_OWN |
+ EQOS_TDES3_RX_IOC | EQOS_TDES3_RX_BUF1V);
}
static int
@@ -747,7 +747,7 @@ eqos_rxintr(struct eqos_softc *sc, int q
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
tdes3 = le32toh(sc->sc_rx.desc_ring[index].tdes3);
- if ((tdes3 & EQOS_TDES3_OWN) != 0) {
+ if ((tdes3 & EQOS_TDES3_RX_OWN) != 0) {
break;
}
@@ -757,7 +757,7 @@ eqos_rxintr(struct eqos_softc *sc, int q
bus_dmamap_unload(sc->sc_dmat,
sc->sc_rx.buf_map[index].map);
- len = tdes3 & EQOS_TDES3_LENGTH_MASK;
+ len = tdes3 & EQOS_TDES3_RX_LENGTH_MASK;
if (len != 0) {
m = sc->sc_rx.buf_map[index].mbuf;
m_set_rcvif(m, ifp);
@@ -815,7 +815,7 @@ eqos_txintr(struct eqos_softc *sc, int q
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
desc = &sc->sc_tx.desc_ring[i];
tdes3 = le32toh(desc->tdes3);
- if ((tdes3 & EQOS_TDES3_OWN) != 0) {
+ if ((tdes3 & EQOS_TDES3_TX_OWN) != 0) {
break;
}
bmap = &sc->sc_tx.buf_map[i];
@@ -837,13 +837,13 @@ eqos_txintr(struct eqos_softc *sc, int q
ifp->if_flags &= ~IFF_OACTIVE;
/* Last descriptor in a packet contains DMA status */
- if ((tdes3 & EQOS_TDES3_LD) != 0) {
- if ((tdes3 & EQOS_TDES3_DE) != 0) {
+ if ((tdes3 & EQOS_TDES3_TX_LD) != 0) {
+ if ((tdes3 & EQOS_TDES3_TX_DE) != 0) {
device_printf(sc->sc_dev,
"TX [%u] desc error: 0x%08x\n",
i, tdes3);
if_statinc(ifp, if_oerrors);
- } else if ((tdes3 & EQOS_TDES3_ES) != 0) {
+ } else if ((tdes3 & EQOS_TDES3_TX_ES) != 0) {
device_printf(sc->sc_dev,
"TX [%u] tx error: 0x%08x\n",
i, tdes3);
Index: src/sys/dev/ic/dwc_eqos_reg.h
diff -u src/sys/dev/ic/dwc_eqos_reg.h:1.5 src/sys/dev/ic/dwc_eqos_reg.h:1.6
--- src/sys/dev/ic/dwc_eqos_reg.h:1.5 Tue Aug 23 05:41:46 2022
+++ src/sys/dev/ic/dwc_eqos_reg.h Wed Aug 24 19:21:41 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.5 2022/08/23 05:41:46 ryo Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.6 2022/08/24 19:21:41 ryo Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -287,16 +287,27 @@ struct eqos_dma_desc {
uint32_t tdes0;
uint32_t tdes1;
uint32_t tdes2;
-#define EQOS_TDES2_IOC (1U << 31) /* TX */
+#define EQOS_TDES2_TX_IOC (1U << 31) /* TX */
uint32_t tdes3;
-#define EQOS_TDES3_OWN (1U << 31) /* TX and RX */
-#define EQOS_TDES3_IOC (1U << 30) /* RX */
-#define EQOS_TDES3_FD (1U << 29) /* TX */
-#define EQOS_TDES3_LD (1U << 28) /* TX */
-#define EQOS_TDES3_BUF1V (1U << 24) /* RX */
-#define EQOS_TDES3_DE (1U << 23) /* TX (WB) */
-#define EQOS_TDES3_ES (1U << 15) /* TX (WB) */
-#define EQOS_TDES3_LENGTH_MASK 0x7FFFU /* RX */
+#define EQOS_TDES3_TX_OWN (1U << 31) /* TX */
+#define EQOS_TDES3_TX_FD (1U << 29) /* TX */
+#define EQOS_TDES3_TX_LD (1U << 28) /* TX */
+#define EQOS_TDES3_TX_DE (1U << 23) /* TX (WB) */
+#define EQOS_TDES3_TX_ES (1U << 15) /* TX (WB) */
+#define EQOS_TDES3_RX_OWN (1U << 31) /* RX */
+#define EQOS_TDES3_RX_IOC (1U << 30) /* RX */
+#define EQOS_TDES3_RX_BUF1V (1U << 24) /* RX */
+#define EQOS_TDES3_RX_CTXT (1U << 30) /* RX (WB) */
+#define EQOS_TDES3_RX_FD (1U << 29) /* RX (WB) */
+#define EQOS_TDES3_RX_LD (1U << 28) /* RX (WB) */
+#define EQOS_TDES3_RX_CE (1U << 24) /* RX (WB) */
+#define EQOS_TDES3_RX_GP (1U << 23) /* RX (WB) */
+#define EQOS_TDES3_RX_RWT (1U << 22) /* RX (WB) */
+#define EQOS_TDES3_RX_OE (1U << 21) /* RX (WB) */
+#define EQOS_TDES3_RX_RE (1U << 20) /* RX (WB) */
+#define EQOS_TDES3_RX_DE (1U << 19) /* RX (WB) */
+#define EQOS_TDES3_RX_ES (1U << 15) /* RX (WB) */
+#define EQOS_TDES3_RX_LENGTH_MASK 0x7FFFU /* RX */
} __aligned (64);
#endif /* !_DWC_EQOS_REG_H */
