Module Name: src
Committed By: ryo
Date: Sat Dec 3 20:24:21 UTC 2022
Modified Files:
src/sys/arch/arm/include: armreg.h
src/sys/dev/tprof: tprof_armv7.c
Log Message:
move ARMv7 PMC register definitions to armreg.h from tprof_armv7.c
To generate a diff of this commit:
cvs rdiff -u -r1.135 -r1.136 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/dev/tprof/tprof_armv7.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.135 src/sys/arch/arm/include/armreg.h:1.136
--- src/sys/arch/arm/include/armreg.h:1.135 Fri May 20 19:34:22 2022
+++ src/sys/arch/arm/include/armreg.h Sat Dec 3 20:24:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.135 2022/05/20 19:34:22 andvar Exp $ */
+/* $NetBSD: armreg.h,v 1.136 2022/12/03 20:24:21 ryo Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -485,6 +485,26 @@
#define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */
#define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */
+/* ARMv7 PMCR, Performance Monitor Control Register */
+#define PMCR_N __BITS(15,11)
+#define PMCR_D __BIT(3)
+#define PMCR_E __BIT(0)
+
+/* ARMv7 INTEN{SET,CLR}, Performance Monitors Interrupt Enable Set register */
+#define PMINTEN_C __BIT(31)
+#define PMINTEN_P __BITS(30,0)
+#define PMCNTEN_C __BIT(31)
+#define PMCNTEN_P __BITS(30,0)
+
+/* ARMv7 PMOVSR, Performance Monitors Overflow Flag Status Register */
+#define PMOVS_C __BIT(31)
+#define PMOVS_P __BITS(30,0)
+
+/* ARMv7 PMXEVTYPER, Performance Monitors Event Type Select Register */
+#define PMEVTYPER_P __BIT(31)
+#define PMEVTYPER_U __BIT(30)
+#define PMEVTYPER_EVTCOUNT __BITS(7,0)
+
/* Defines for ARM CORTEX performance counters */
#define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */
#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
Index: src/sys/dev/tprof/tprof_armv7.c
diff -u src/sys/dev/tprof/tprof_armv7.c:1.10 src/sys/dev/tprof/tprof_armv7.c:1.11
--- src/sys/dev/tprof/tprof_armv7.c:1.10 Thu Dec 1 00:32:52 2022
+++ src/sys/dev/tprof/tprof_armv7.c Sat Dec 3 20:24:21 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_armv7.c,v 1.10 2022/12/01 00:32:52 ryo Exp $ */
+/* $NetBSD: tprof_armv7.c,v 1.11 2022/12/03 20:24:21 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.10 2022/12/01 00:32:52 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.11 2022/12/03 20:24:21 ryo Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -42,22 +42,6 @@ __KERNEL_RCSID(0, "$NetBSD: tprof_armv7.
#include <dev/tprof/tprof_armv7.h>
-#define PMCR_N __BITS(15,11)
-#define PMCR_D __BIT(3)
-#define PMCR_E __BIT(0)
-
-#define PMINTEN_C __BIT(31)
-#define PMINTEN_P __BITS(30,0)
-#define PMCNTEN_C __BIT(31)
-#define PMCNTEN_P __BITS(30,0)
-
-#define PMOVS_C __BIT(31)
-#define PMOVS_P __BITS(30,0)
-
-#define PMEVTYPER_P __BIT(31)
-#define PMEVTYPER_U __BIT(30)
-#define PMEVTYPER_EVTCOUNT __BITS(7,0)
-
static uint16_t cortexa9_events[] = {
0x40, 0x41, 0x42,
0x50, 0x51,
