Module Name: src Committed By: riastradh Date: Wed Mar 1 08:18:24 UTC 2023
Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Optimization: Omit needless membar when triggering softint. When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.