Module Name: src Committed By: tsutsui Date: Fri Nov 17 23:08:27 UTC 2023
Modified Files: src/external/gpl3/binutils.old/dist/gas/config: tc-mips.c Log Message: binutils.old: apply the same fix for mips gas from binutils. > binutils: fix gas that doesn't handle MIPS1 FPR load hazard correctly. > Fixes PR/57680. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 \ src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c diff -u src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c:1.7 src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c:1.8 --- src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c:1.7 Fri Dec 23 17:09:21 2022 +++ src/external/gpl3/binutils.old/dist/gas/config/tc-mips.c Fri Nov 17 23:08:27 2023 @@ -6529,8 +6529,8 @@ insns_between (const struct mips_cl_insn /* Itbl support may require additional care here. FIXME! Need to modify this to include knowledge about user specified delays! */ - else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) - || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) + if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) + || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) { /* Handle cases where INSN1 writes to a known general coprocessor register. There must be a one instruction delay before INSN2