Module Name:    src
Committed By:   andvar
Date:           Fri Feb  2 22:19:13 UTC 2024

Modified Files:
        src/sys/arch/hp300/dev: topcatreg.h
        src/sys/arch/hp300/stand/common: grf_tcreg.h
        src/sys/dev/ic: aacreg.h
        src/sys/dev/pci: pcireg.h

Log Message:
s/Staus/Status/ in comments.


To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/hp300/dev/topcatreg.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/hp300/stand/common/grf_tcreg.h
cvs rdiff -u -r1.14 -r1.15 src/sys/dev/ic/aacreg.h
cvs rdiff -u -r1.168 -r1.169 src/sys/dev/pci/pcireg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/hp300/dev/topcatreg.h
diff -u src/sys/arch/hp300/dev/topcatreg.h:1.3 src/sys/arch/hp300/dev/topcatreg.h:1.4
--- src/sys/arch/hp300/dev/topcatreg.h:1.3	Sun Jan 15 06:19:45 2023
+++ src/sys/arch/hp300/dev/topcatreg.h	Fri Feb  2 22:19:13 2024
@@ -1,5 +1,5 @@
 /*	$OpenBSD: topcatreg.h,v 1.2 2005/01/24 21:36:39 miod Exp $	*/
-/*	$NetBSD: topcatreg.h,v 1.3 2023/01/15 06:19:45 tsutsui Exp $	*/
+/*	$NetBSD: topcatreg.h,v 1.4 2024/02/02 22:19:13 andvar Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -95,7 +95,7 @@ struct tcboxfb {
 	uint16_t wheight;		/* block mover pixel height   0x4106 */
   /* Catseye */
 	uint8_t f19[0x4206-0x4106-2];
-	uint16_t rug_cmdstat;		/* RUG Command/Staus	      0x4206 */
+	uint16_t rug_cmdstat;		/* RUG Command/Status	      0x4206 */
 	uint8_t f20[0x4510-0x4206-2];
 	uint16_t vb_select;		/* Vector/BitBlt Select	      0x4510 */
 	uint16_t tcntrl;		/* Three Operand Control      0x4512 */

Index: src/sys/arch/hp300/stand/common/grf_tcreg.h
diff -u src/sys/arch/hp300/stand/common/grf_tcreg.h:1.2 src/sys/arch/hp300/stand/common/grf_tcreg.h:1.3
--- src/sys/arch/hp300/stand/common/grf_tcreg.h:1.2	Tue Feb  8 20:20:14 2011
+++ src/sys/arch/hp300/stand/common/grf_tcreg.h	Fri Feb  2 22:19:13 2024
@@ -1,4 +1,4 @@
-/*	$NetBSD: grf_tcreg.h,v 1.2 2011/02/08 20:20:14 rmind Exp $	*/
+/*	$NetBSD: grf_tcreg.h,v 1.3 2024/02/02 22:19:13 andvar Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -119,7 +119,7 @@ struct tcboxfb {
   vu_short 	wheight;		/* block mover pixel height   0x4106 */
   /* Catseye */
   u_char	f19[0x4206-0x4106-2];
-  vu_short	rug_cmdstat;		/* RUG Command/Staus	      0x4206 */
+  vu_short	rug_cmdstat;		/* RUG Command/Status	      0x4206 */
   u_char	f20[0x4510-0x4206-2];
   vu_short	vb_select;		/* Vector/BitBlt Select	      0x4510 */
   vu_short	tcntrl;			/* Three Operand Control      0x4512 */

Index: src/sys/dev/ic/aacreg.h
diff -u src/sys/dev/ic/aacreg.h:1.14 src/sys/dev/ic/aacreg.h:1.15
--- src/sys/dev/ic/aacreg.h:1.14	Fri Dec 10 20:36:03 2021
+++ src/sys/dev/ic/aacreg.h	Fri Feb  2 22:19:13 2024
@@ -1,4 +1,4 @@
-/*	$NetBSD: aacreg.h,v 1.14 2021/12/10 20:36:03 andvar Exp $	*/
+/*	$NetBSD: aacreg.h,v 1.15 2024/02/02 22:19:13 andvar Exp $	*/
 
 /*-
  * Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
@@ -576,7 +576,7 @@ struct aac_ctcfg_resp {
 } __packed;
 
 /*
- * 'Ioctl' commads
+ * 'Ioctl' commands
  */
 #define AAC_SCSI_MAX_PORTS	10
 #define AAC_BUS_NO_EXIST	0
@@ -1118,7 +1118,7 @@ struct aac_fib {
 /*
  *  Adapter Status Register
  *
- *  Phase Staus mailbox is 32bits:
+ *  Phase Status mailbox is 32bits:
  *  <31:16> = Phase Status
  *  <15:0>  = Phase
  *

Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.168 src/sys/dev/pci/pcireg.h:1.169
--- src/sys/dev/pci/pcireg.h:1.168	Mon Oct 17 03:05:32 2022
+++ src/sys/dev/pci/pcireg.h	Fri Feb  2 22:19:13 2024
@@ -1,4 +1,4 @@
-/*	$NetBSD: pcireg.h,v 1.168 2022/10/17 03:05:32 mrg Exp $	*/
+/*	$NetBSD: pcireg.h,v 1.169 2024/02/02 22:19:13 andvar Exp $	*/
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -2116,7 +2116,7 @@ struct pci_rom {
 #define	PCI_DPCCTL_DLACTECOR	__BIT(23)      /* DL_Active ERR_COR Enable */
 
 #define	PCI_DPC_STATESID 0x08	/* Status and Error Source ID Register */
-#define	PCI_DPCSTAT_TSTAT	__BIT(0)       /* DPC Trigger Staus */
+#define	PCI_DPCSTAT_TSTAT	__BIT(0)       /* DPC Trigger Status */
 #define	PCI_DPCSTAT_TREASON	__BITS(2, 1)   /* DPC Trigger Reason */
 #define	PCI_DPCSTAT_ISTAT	__BIT(3)       /* DPC Interrupt Status */
 #define	PCI_DPCSTAT_RPBUSY	__BIT(4)       /* DPC RP Busy */

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