Module Name: src
Committed By: nisimura
Date: Fri Jul 3 10:31:19 UTC 2009
Modified Files:
src/sys/arch/sandpoint/stand/netboot: brdsetup.c globals.h main.c tlp.c
Log Message:
- adapt KURBOX/HG arrangements, requested and tested by kiyohara.
- make tlp.c suited for ADMTek/Infineon AN983B/BX.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/sandpoint/stand/netboot/brdsetup.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/sandpoint/stand/netboot/globals.h
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/sandpoint/stand/netboot/main.c \
src/sys/arch/sandpoint/stand/netboot/tlp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sandpoint/stand/netboot/brdsetup.c
diff -u src/sys/arch/sandpoint/stand/netboot/brdsetup.c:1.7 src/sys/arch/sandpoint/stand/netboot/brdsetup.c:1.8
--- src/sys/arch/sandpoint/stand/netboot/brdsetup.c:1.7 Fri Jun 12 00:24:33 2009
+++ src/sys/arch/sandpoint/stand/netboot/brdsetup.c Fri Jul 3 10:31:19 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: brdsetup.c,v 1.7 2009/06/12 00:24:33 nisimura Exp $ */
+/* $NetBSD: brdsetup.c,v 1.8 2009/07/03 10:31:19 nisimura Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -87,6 +87,22 @@
consname = "eumb";
consport = 0x4600;
consspeed = 57600;
+ if (pcifinddev(0x10ec, 0x8169, &pcib) == 0) /* KURO-BOX/HG */
+ ticks_per_sec = 133000000 / 4;
+
+ /* Stop Watchdog */
+ uartbase = 0xfc000000 + 0x4500;
+ div = (ticks_per_sec * 4) / 9600 / 16;
+ UART_WRITE(DCR, 0x01); /* 2 independent UART */
+ UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
+ UART_WRITE(FCR, 0x00);
+ UART_WRITE(DMB, div >> 8);
+ UART_WRITE(DLB, div & 0xff);
+ UART_WRITE(LCR, 0x03 | 0x18); /* 8 E 1 */
+ UART_WRITE(MCR, 0x03); /* RTS DTR */
+ UART_WRITE(FCR, 0x07); /* FIFO_EN | RXSR | TXSR */
+ UART_WRITE(IER, 0x00); /* make sure INT disabled */
+ printf("AAAAFFFFJJJJ>>>>VVVV>>>>ZZZZVVVVKKKK");
}
/* now prepare serial console */
@@ -94,7 +110,7 @@
uartbase = 0xfe000000 + consport; /* 0x3f8, 0x2f8 */
else {
uartbase = 0xfc000000 + consport; /* 0x4500, 0x4600 */
- div = (TICKS_PER_SEC * 4) / consspeed / 16;
+ div = (ticks_per_sec * 4) / consspeed / 16;
UART_WRITE(DCR, 0x01); /* 2 independent UART */
UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
UART_WRITE(FCR, 0x00);
Index: src/sys/arch/sandpoint/stand/netboot/globals.h
diff -u src/sys/arch/sandpoint/stand/netboot/globals.h:1.9 src/sys/arch/sandpoint/stand/netboot/globals.h:1.10
--- src/sys/arch/sandpoint/stand/netboot/globals.h:1.9 Fri Jun 12 00:24:33 2009
+++ src/sys/arch/sandpoint/stand/netboot/globals.h Fri Jul 3 10:31:19 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: globals.h,v 1.9 2009/06/12 00:24:33 nisimura Exp $ */
+/* $NetBSD: globals.h,v 1.10 2009/07/03 10:31:19 nisimura Exp $ */
/* clock feed */
#ifndef TICKS_PER_SEC
@@ -17,6 +17,7 @@
extern char *consname;
extern int consport;
extern int consspeed;
+extern int ticks_per_sec;
unsigned mpc107memsize(void);
Index: src/sys/arch/sandpoint/stand/netboot/main.c
diff -u src/sys/arch/sandpoint/stand/netboot/main.c:1.22 src/sys/arch/sandpoint/stand/netboot/main.c:1.23
--- src/sys/arch/sandpoint/stand/netboot/main.c:1.22 Fri Jun 12 00:24:33 2009
+++ src/sys/arch/sandpoint/stand/netboot/main.c Fri Jul 3 10:31:19 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: main.c,v 1.22 2009/06/12 00:24:33 nisimura Exp $ */
+/* $NetBSD: main.c,v 1.23 2009/07/03 10:31:19 nisimura Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -58,6 +58,7 @@
char *consname = CONSNAME;
int consport = CONSPORT;
int consspeed = CONSSPEED;
+int ticks_per_sec = TICKS_PER_SEC;
void
main(void)
@@ -135,7 +136,7 @@
snprintf(bi_cons.devname, sizeof(bi_cons.devname), consname);
bi_cons.addr = consport;
bi_cons.speed = consspeed;
- bi_clk.ticks_per_sec = TICKS_PER_SEC;
+ bi_clk.ticks_per_sec = ticks_per_sec;
snprintf(bi_path.bootpath, sizeof(bi_path.bootpath), bootfile);
snprintf(bi_rdev.devname, sizeof(bi_rdev.devname), rootdev);
bi_rdev.cookie = tag; /* PCI tag for fxp netboot case */
Index: src/sys/arch/sandpoint/stand/netboot/tlp.c
diff -u src/sys/arch/sandpoint/stand/netboot/tlp.c:1.22 src/sys/arch/sandpoint/stand/netboot/tlp.c:1.23
--- src/sys/arch/sandpoint/stand/netboot/tlp.c:1.22 Sun Jan 25 03:39:28 2009
+++ src/sys/arch/sandpoint/stand/netboot/tlp.c Fri Jul 3 10:31:19 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: tlp.c,v 1.22 2009/01/25 03:39:28 nisimura Exp $ */
+/* $NetBSD: tlp.c,v 1.23 2009/07/03 10:31:19 nisimura Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -41,13 +41,13 @@
/*
* - reverse endian access for CSR register.
- * - no vtophys() translation, vaddr_t == paddr_t.
+ * - no vtophys() translation, vaddr_t == paddr_t.
* - PIPT writeback cache aware.
*/
#define CSR_READ(l, r) in32rb((l)->csr+(r))
-#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
-#define VTOPHYS(va) (uint32_t)(va)
-#define DEVTOV(pa) (uint32_t)(pa)
+#define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
+#define VTOPHYS(va) (uint32_t)(va)
+#define DEVTOV(pa) (uint32_t)(pa)
#define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
#define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz))
#define DELAY(n) delay(n)
@@ -60,7 +60,6 @@
#define T0_ES (1U<<15) /* Tx error summary */
#define T1_LS (1U<<30) /* last segment */
#define T1_FS (1U<<29) /* first segment */
-#define T1_SET (1U<<27) /* "setup packet" */
#define T1_TER (1U<<25) /* end of ring mark */
#define T1_TCH (1U<<24) /* TDES3 points the next desc */
#define T1_TBS_MASK 0x7ff /* segment size 10:0 */
@@ -73,47 +72,40 @@
#define R0_FLMASK 0x3fff0000 /* frame length 29:16 */
#define R1_RBS_MASK 0x7ff /* segment size 10:0 */
-#define TLP_BMR 0x00 /* 0: bus mode */
-#define BMR_RST 01
-#define BMR_CAL8 0x00004000 /* 32B cache alignment */
-#define BMR_CAL16 0x00008000 /* 64B */
-#define BMR_CAL32 0x0000c000 /* 128B */
-#define BMR_CAL 0x0000c000
-#define TLP_TPD 0x08 /* 1: instruct Tx to start */
-#define TLP_RPD 0x10 /* 2: instruct Rx to start */
-#define TLP_RRBA 0x18 /* 3: Rx descriptor base */
-#define TLP_TRBA 0x20 /* 4: Tx descriptor base */
-#define TLP_STS 0x28 /* 5: status */
-#define STS_TS 0x00700000 /* Tx status */
-#define STS_RS 0x000e0000 /* Rx status */
-#define TLP_OMR 0x30 /* 6: operation mode */
-#define OMR_SDP (1U<<25) /* always ON */
-#define OMR_PS (1U<<18) /* port select */
-#define OMR_PM (1U<< 6) /* promiscuous */
-#define OMR_TEN (1U<<13) /* instruct start/stop Tx */
-#define OMR_REN (1U<< 1) /* instruct start/stop Rx */
-#define OMR_FD (1U<< 9) /* FDX */
-#define TLP_IEN 0x38 /* 7: interrupt enable mask */
-#define TLP_APROM 0x48 /* 9: SEEPROM and MII management */
-#define SROM_RD (1U <<14) /* read operation */
-#define SROM_WR (1U <<13) /* write openration */
-#define SROM_SR (1U <<11) /* SEEPROM select */
-#define TLP_CSR12 0x60 /* 12: SIA status */
+#define PAR_CSR0 0x00 /* bus mode */
+#define PAR_DEFAULTS 0x00001000 /* PDF sez it should be ... */
+#define PAR_SWR 01
+#define TDR_CSR1 0x08 /* T0_OWN poll demand */
+#define RDR_CSR2 0x10 /* R0_OWN poll demand */
+#define RDB_CSR3 0x18 /* Rx descriptor base */
+#define TDB_CSR4 0x20 /* Tx descriptor base */
+#define SR_CSR5 0x28 /* interrupt stauts */
+#define NAR_CSR6 0x30 /* operation mode */
+#define NAR_NOSQE (1U<<19) /* _not_ use SQE signal */
+#define NAR_TEN (1U<<13) /* instruct start/stop Tx */
+#define NAR_REN (1U<< 1) /* instruct start/stop Rx */
+#define IER_CSR7 0x38 /* interrupt enable mask */
+#define SPR_CSR9 0x48 /* SEEPROM and MII management */
+#define MII_MDI (1U<<19) /* 0/1 presense after read op */
+#define MII_MIDIR (1U<<18) /* 1 for PHY->HOST */
+#define MII_MDO (1U<<17) /* 0/1 for write op */
+#define MII_MDC (1U<<16) /* MDIO clock */
+#define SROM_RD (1U<<14) /* read operation */
+#define SROM_WR (1U<<13) /* write openration */
+#define SROM_SR (1U<<11) /* SEEPROM select */
+#define PAR0_CSR25 0xa4 /* MAC 3:0 */
+#define PAR1_CSR26 0xa8 /* MAC 5:4 */
#define FRAMESIZE 1536
struct local {
- struct desc txd;
+ struct desc txd[2];
struct desc rxd[2];
- uint8_t txstore[192];
uint8_t rxstore[2][FRAMESIZE];
- unsigned csr, omr, rx;
- unsigned sromsft;
+ unsigned csr, omr, tx, rx;
unsigned phy, bmsr, anlpar;
};
-static void size_srom(struct local *);
-static int read_srom(struct local *, int);
static unsigned mii_read(struct local *, int, int);
static void mii_write(struct local *, int, int, int);
static void mii_initphy(struct local *);
@@ -126,7 +118,7 @@
v = pcicfgread(tag, PCI_ID_REG);
switch (v) {
- case PCI_DEVICE(0x1011, 0x0009):
+ case PCI_DEVICE(0x1317, 0x0985): /* ADMTek/Infineon 983B/BX */
return 1;
}
return 0;
@@ -139,39 +131,32 @@
struct local *l;
struct desc *txd, *rxd;
uint8_t *en;
- uint32_t *p;
- l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
+ l = ALLOC(struct local, 2 * sizeof(struct desc)); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */
- val = CSR_READ(l, TLP_BMR);
- CSR_WRITE(l, TLP_BMR, val | BMR_RST);
- DELAY(1000);
- val &= ~BMR_CAL;
- switch (pcicfgread(tag, 0x0c) & 0xff) {
- case 32:
- val |= BMR_CAL32; break;
- case 16:
- val |= BMR_CAL16; break;
- case 8:
- default:
- val |= BMR_CAL8; break;
- }
- CSR_WRITE(l, TLP_BMR, val);
- DELAY(1000);
- (void)CSR_READ(l, TLP_BMR);
-
- l->omr = OMR_PS | OMR_SDP;
- CSR_WRITE(l, TLP_OMR, l->omr);
- CSR_WRITE(l, TLP_STS, ~0);
- CSR_WRITE(l, TLP_IEN, 0);
+ CSR_WRITE(l, PAR_CSR0, PAR_SWR);
+ i = 100;
+ do {
+ DELAY(10);
+ } while (i-- > 0 && (CSR_READ(l, PAR_CSR0) & PAR_SWR) != 0);
+ CSR_WRITE(l, PAR_CSR0, PAR_DEFAULTS);
+
+ l->omr = NAR_NOSQE;
+ CSR_WRITE(l, NAR_CSR6, l->omr);
+ CSR_WRITE(l, SR_CSR5, ~0);
+ CSR_WRITE(l, IER_CSR7, 0);
- size_srom(l);
en = data;
- val = read_srom(l, 20/2+0); en[0] = val; en[1] = val >> 8;
- val = read_srom(l, 20/2+1); en[2] = val; en[3] = val >> 8;
- val = read_srom(l, 20/2+2); en[4] = val; en[5] = val >> 8;
+ val = CSR_READ(l, PAR0_CSR25);
+ en[0] = val & 0xff;
+ en[1] = (val >> 8) & 0xff;
+ en[2] = (val >> 16) & 0xff;
+ en[3] = (val >> 24) & 0xff;
+ val = CSR_READ(l, PAR1_CSR26);
+ en[4] = val & 0xff;
+ en[5] = (val >> 8) & 0xff;
#if 1
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
@@ -180,43 +165,25 @@
mii_initphy(l);
mii_dealan(l, 5);
- txd = &l->txd;
+ txd = &l->txd[0];
+ txd[1].xd1 = htole32(T1_TER);
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
- rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
+ rxd[0].xd1 = htole32(FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
- rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
- /* R1_RER neglects xd3 */
- l->rx = 0;
-
- /* "setup frame" to have own station address */
- txd = &l->txd;
- txd->xd3 = htole32(VTOPHYS(txd));
- txd->xd2 = htole32(VTOPHYS(l->txstore));
- txd->xd1 = htole32(T1_SET | sizeof(l->txstore));
- txd->xd0 = htole32(T0_OWN);
- p = (uint32_t *)l->txstore;
- p[0] = htole32(en[1] << 8 | en[0]);
- p[1] = htole32(en[3] << 8 | en[2]);
- p[2] = htole32(en[5] << 8 | en[4]);
- for (i = 1; i < 16; i++)
- memcpy(&p[3 * i], &p[0], 3 * sizeof(p[0]));
+ l->tx = l->rx = 0;
/* make sure the entire descriptors transfered to memory */
wbinv(l, sizeof(struct local));
- CSR_WRITE(l, TLP_TRBA, VTOPHYS(txd));
- CSR_WRITE(l, TLP_RRBA, VTOPHYS(rxd));
+ CSR_WRITE(l, TDB_CSR4, VTOPHYS(txd));
+ CSR_WRITE(l, RDB_CSR3, VTOPHYS(rxd));
/* start Tx/Rx */
- l->omr |= OMR_FD | OMR_TEN | OMR_REN;
- CSR_WRITE(l, TLP_OMR, l->omr);
- CSR_WRITE(l, TLP_TPD, 01);
- /* could wait for "setup frame" completion */
- CSR_WRITE(l, TLP_RPD, 01);
+ CSR_WRITE(l, NAR_CSR6, l->omr | NAR_TEN | NAR_REN);
return l;
}
@@ -228,14 +195,14 @@
volatile struct desc *txd;
unsigned txstat, loop;
- /* send a single frame with no T1_TER|T1_TCH designation */
wbinv(buf, len);
- txd = &l->txd;
+ txd = &l->txd[l->tx];
txd->xd2 = htole32(VTOPHYS(buf));
- txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
+ txd->xd1 &= htole32(T1_TER);
+ txd->xd1 |= htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
txd->xd0 = htole32(T0_OWN);
wbinv(txd, sizeof(struct desc));
- CSR_WRITE(l, TLP_TPD, 01);
+ CSR_WRITE(l, TDR_CSR1, 01);
loop = 100;
do {
txstat = le32toh(txd->xd0);
@@ -247,6 +214,7 @@
printf("xmit failed\n");
return -1;
done:
+ l->tx ^= 1;
return len;
}
@@ -259,7 +227,9 @@
uint8_t *ptr;
bound = 1000 * timo;
+#if 0
printf("recving with %u sec. timeout\n", timo);
+#endif
again:
rxd = &l->rxd[l->rx];
do {
@@ -276,127 +246,68 @@
rxd->xd0 = htole32(R0_OWN);
wbinv(rxd, sizeof(struct desc));
l->rx ^= 1;
- CSR_WRITE(l, TLP_RPD, 01);
goto again;
}
/* good frame */
- len = ((rxstat & R0_FLMASK) >> 16) - 4 /* HASFCS */;
- if (len > maxlen)
- len = maxlen;
+ len = ((rxstat & R0_FLMASK) >> 16) - 4 /* HASFCS */;
+ if (len > maxlen)
+ len = maxlen;
ptr = l->rxstore[l->rx];
- inv(ptr, len);
- memcpy(buf, ptr, len);
+ inv(ptr, len);
+ memcpy(buf, ptr, len);
rxd->xd0 = htole32(R0_OWN);
wbinv(rxd, sizeof(struct desc));
l->rx ^= 1;
- CSR_WRITE(l, TLP_OMR, l->omr); /* necessary? */
return len;
}
-static void
-size_srom(struct local *l)
-{
- /* determine 8/6 bit addressing SEEPROM */
- l->sromsft = 8;
- l->sromsft = (read_srom(l, 255) & 0x40000) ? 8 : 6;
-}
-
/*
- * bare SEEPROM access with bitbang'ing
+ * bare MII access with bitbang'ing
*/
#define R110 6 /* SEEPROM/MDIO read op */
#define W101 5 /* SEEPROM/MDIO write op */
-#define CS (1U << 0) /* hold chip select */
+#define CS (1U << 0) /* hold chip select */
#define CLK (1U << 1) /* clk bit */
#define D1 (1U << 2) /* bit existence */
-#define VV (1U << 3) /* taken 0/1 from SEEPROM */
-
-static int
-read_srom(struct local *l, int off)
-{
- unsigned data, v, i;
-
- data = off & 0xff; /* A7-A0 */
- data |= R110 << l->sromsft; /* 110 for READ */
-
- v = SROM_RD | SROM_SR;
- CSR_WRITE(l, TLP_APROM, v);
- v |= CS; /* hold CS */
- CSR_WRITE(l, TLP_APROM, v);
-
- /* instruct R110 op. at off in MSB first order */
- for (i = (1 << (l->sromsft + 2)); i != 0; i >>= 1) {
- if (data & i)
- v |= D1;
- else
- v &= ~D1;
- CSR_WRITE(l, TLP_APROM, v);
- DELAY(10);
- CSR_WRITE(l, TLP_APROM, v | CLK);
- DELAY(10);
- }
- v &= ~D1;
-
- /* read 16bit quantity in MSB first order */
- data = 0;
- for (i = 0; i < 16; i++) {
- CSR_WRITE(l, TLP_APROM, v);
- DELAY(10);
- CSR_WRITE(l, TLP_APROM, v | CLK);
- DELAY(10);
- data = (data << 1) | !!(CSR_READ(l, TLP_APROM) & VV);
- }
- /* turn off chip select */
- CSR_WRITE(l, TLP_APROM, 0);
-
- return data;
-}
-
-/*
- * bare MII access with bitbang'ing
- */
-#define MDI (1U << 19) /* taken 0/1 from MDIO */
-#define MII (1U << 18) /* read operation */
-#define MDO (1U << 17) /* bit existence */
-#define MDC (1U << 16) /* clock bit */
+#define VV (1U << 3) /* taken 0/1 from SEEPROM */
static unsigned
mii_read(struct local *l, int phy, int reg)
{
- unsigned data, v, i;
+ unsigned data, rv, v, i;
data = (R110 << 10) | (phy << 5) | reg;
- CSR_WRITE(l, TLP_APROM, MDO);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO);
for (i = 0; i < 32; i++) {
- CSR_WRITE(l, TLP_APROM, MDO | MDC);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO | MII_MDC);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, MDO);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO);
DELAY(1);
}
- CSR_WRITE(l, TLP_APROM, 0);
+ CSR_WRITE(l, SPR_CSR9, 0);
v = 0; /* 4OP + 5ADDR + 5REG */
for (i = (1 << 13); i != 0; i >>= 1) {
if (data & i)
- v |= MDO;
+ v |= MII_MDO;
else
- v &= ~MDO;
- CSR_WRITE(l, TLP_APROM, v);
+ v &= ~MII_MDO;
+ CSR_WRITE(l, SPR_CSR9, v);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, v | MDC);
+ CSR_WRITE(l, SPR_CSR9, v | MII_MDC);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, v);
+ CSR_WRITE(l, SPR_CSR9, v);
DELAY(1);
}
- data = 0; /* 2TA + 16MDI */
+ rv = 0; /* 2TA + 16MDI */
for (i = 0; i < 18; i++) {
- CSR_WRITE(l, TLP_APROM, MII);
+ CSR_WRITE(l, SPR_CSR9, MII_MIDIR);
DELAY(1);
- data = (data << 1) | !!(CSR_READ(l, TLP_APROM) & MDI);
- CSR_WRITE(l, TLP_APROM, MII | MDC);
+ rv = (data << 1) | !!(CSR_READ(l, SPR_CSR9) & MII_MDI);
+ CSR_WRITE(l, SPR_CSR9, MII_MIDIR | MII_MDC);
DELAY(1);
}
- CSR_WRITE(l, TLP_APROM, 0);
- return data & 0xffff;
+ CSR_WRITE(l, SPR_CSR9, 0);
+ return rv & 0xffff;
}
static void
@@ -406,28 +317,28 @@
data = (W101 << 28) | (phy << 23) | (reg << 18) | (02 << 16);
data |= val & 0xffff;
- CSR_WRITE(l, TLP_APROM, MDO);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO);
for (i = 0; i < 32; i++) {
- CSR_WRITE(l, TLP_APROM, MDO | MDC);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO | MII_MDC);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, MDO);
+ CSR_WRITE(l, SPR_CSR9, MII_MDO);
DELAY(1);
}
- CSR_WRITE(l, TLP_APROM, 0);
+ CSR_WRITE(l, SPR_CSR9, 0);
v = 0; /* 4OP + 5ADDR + 5REG + 2TA + 16DATA */
for (i = (1 << 31); i != 0; i >>= 1) {
if (data & i)
- v |= MDO;
+ v |= MII_MDO;
else
- v &= ~MDO;
- CSR_WRITE(l, TLP_APROM, v);
+ v &= ~MII_MDO;
+ CSR_WRITE(l, SPR_CSR9, v);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, v | MDC);
+ CSR_WRITE(l, SPR_CSR9, v | MII_MDC);
DELAY(1);
- CSR_WRITE(l, TLP_APROM, v);
+ CSR_WRITE(l, SPR_CSR9, v);
DELAY(1);
}
- CSR_WRITE(l, TLP_APROM, 0);
+ CSR_WRITE(l, SPR_CSR9, 0);
}
#define MII_BMCR 0x00 /* Basic mode control register (rw) */
