Module Name: src
Committed By: matt
Date: Tue Sep 15 05:12:53 UTC 2009
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h
src/sys/arch/mips/mips [matt-nb5-mips64]: db_interface.c
Log Message:
Add a CPU_MIPS_NO_LLADDR flag / MIPS_HAS_LLADDR macro. And use to determine
whether to printf lladdr COP0 register
To generate a diff of this commit:
cvs rdiff -u -r1.90.16.2 -r1.90.16.3 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.64.16.5 -r1.64.16.6 src/sys/arch/mips/mips/db_interface.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.90.16.2 src/sys/arch/mips/include/cpu.h:1.90.16.3
--- src/sys/arch/mips/include/cpu.h:1.90.16.2 Tue Sep 8 07:54:52 2009
+++ src/sys/arch/mips/include/cpu.h Tue Sep 15 05:12:53 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.90.16.2 2009/09/08 07:54:52 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.90.16.3 2009/09/15 05:12:53 matt Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -173,6 +173,7 @@
#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */
#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */
#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */
+#define CPU_MIPS_NO_LLADDR 0x1000
#define MIPS_NOT_SUPP 0x8000
#endif /* !_LOCORE */
@@ -239,6 +240,7 @@
#define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu)
#define MIPS_HAS_LLSC (mips_has_llsc)
+#define MIPS_HAS_LLADDR ((mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
/* This test is ... rather bogus */
#define CPUISMIPS3 ((cpu_arch & \
Index: src/sys/arch/mips/mips/db_interface.c
diff -u src/sys/arch/mips/mips/db_interface.c:1.64.16.5 src/sys/arch/mips/mips/db_interface.c:1.64.16.6
--- src/sys/arch/mips/mips/db_interface.c:1.64.16.5 Sun Sep 13 03:31:05 2009
+++ src/sys/arch/mips/mips/db_interface.c Tue Sep 15 05:12:53 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.64.16.5 2009/09/13 03:31:05 cliff Exp $ */
+/* $NetBSD: db_interface.c,v 1.64.16.6 2009/09/15 05:12:53 matt Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.64.16.5 2009/09/13 03:31:05 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.64.16.6 2009/09/15 05:12:53 matt Exp $");
#include "opt_cputype.h" /* which mips CPUs do we support? */
#include "opt_ddb.h"
@@ -507,14 +507,14 @@
#endif
if (MIPS_HAS_LLSC) {
- if (CPUISMIPS64) {
-#if !defined(MIPS64_XLS) /* CP0 reg #17 "reserved" */
- SHOW64(MIPS_COP_0_LLADDR, "lladdr");
- SHOW64(MIPS_COP_0_WATCH_LO, "watchlo");
-#endif
- } else {
- SHOW32(MIPS_COP_0_LLADDR, "lladdr");
- SHOW32(MIPS_COP_0_WATCH_LO, "watchlo");
+ if (MIPS_HAS_LLADDR) {
+ if (CPUIS64BITS) {
+ SHOW64(MIPS_COP_0_LLADDR, "lladdr");
+ SHOW64(MIPS_COP_0_WATCH_LO, "watchlo");
+ } else {
+ SHOW32(MIPS_COP_0_LLADDR, "lladdr");
+ SHOW32(MIPS_COP_0_WATCH_LO, "watchlo");
+ }
}
SHOW32(MIPS_COP_0_WATCH_HI, "watchhi");
