Module Name: src
Committed By: maxv
Date: Fri Aug 10 16:17:30 UTC 2018
Modified Files:
src/sys/arch/arm/arm: cpufunc.c fiq_subr.S
src/sys/arch/arm/arm32: cpu.c fault.c
src/sys/arch/arm/conf: files.arm
src/sys/arch/arm/include: cpuconf.h cpufunc_proto.h
Removed Files:
src/sys/arch/arm/arm: cpufunc_asm_arm3.S
Log Message:
Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.
ok jmcneill@ skrll@
To generate a diff of this commit:
cvs rdiff -u -r1.170 -r1.171 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.4 -r0 src/sys/arch/arm/arm/cpufunc_asm_arm3.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/fiq_subr.S
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/arm/arm32/fault.c
cvs rdiff -u -r1.139 -r1.140 src/sys/arch/arm/conf/files.arm
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/include/cpuconf.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/include/cpufunc_proto.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.170 src/sys/arch/arm/arm/cpufunc.c:1.171
--- src/sys/arch/arm/arm/cpufunc.c:1.170 Thu Jul 12 12:48:50 2018
+++ src/sys/arch/arm/arm/cpufunc.c Fri Aug 10 16:17:29 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.170 2018/07/12 12:48:50 jakllsch Exp $ */
+/* $NetBSD: cpufunc.c,v 1.171 2018/08/10 16:17:29 maxv Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.170 2018/07/12 12:48:50 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.171 2018/08/10 16:17:29 maxv Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -118,174 +118,6 @@ u_int arm_dcache_align_mask;
/* 1 == use cpu_sleep(), 0 == don't */
int cpu_do_powersave;
-#ifdef CPU_ARM2
-struct cpu_functions arm2_cpufuncs = {
- /* CPU functions */
-
- .cf_id = arm2_id,
- .cf_cpwait = cpufunc_nullop,
-
- /* MMU functions */
-
- .cf_control = (void *)cpufunc_nullop,
-
- /* TLB functions */
-
- .cf_tlb_flushID = cpufunc_nullop,
- .cf_tlb_flushID_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushI = cpufunc_nullop,
- .cf_tlb_flushI_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushD = cpufunc_nullop,
- .cf_tlb_flushD_SE = (void *)cpufunc_nullop,
-
- /* Cache operations */
-
- .cf_icache_sync_all = cpufunc_nullop,
- .cf_icache_sync_range = (void *) cpufunc_nullop,
-
- .cf_dcache_wbinv_all = arm3_cache_flush,
- .cf_dcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_dcache_inv_range = (void *)cpufunc_nullop,
- .cf_dcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_sdcache_inv_range = (void *)cpufunc_nullop,
- .cf_sdcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_idcache_wbinv_all = cpufunc_nullop,
- .cf_idcache_wbinv_range = (void *)cpufunc_nullop,
-
- /* Other functions */
-
- .cf_flush_prefetchbuf = cpufunc_nullop,
- .cf_drain_writebuf = cpufunc_nullop,
- .cf_flush_brnchtgt_C = cpufunc_nullop,
- .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
-
- .cf_sleep = (void *)cpufunc_nullop,
-
- /* Soft functions */
-
- .cf_dataabt_fixup = early_abort_fixup,
- .cf_prefetchabt_fixup = cpufunc_null_fixup,
-
- .cf_setup = (void *)cpufunc_nullop
-
-};
-#endif /* CPU_ARM2 */
-
-#ifdef CPU_ARM250
-struct cpu_functions arm250_cpufuncs = {
- /* CPU functions */
-
- .cf_id = arm250_id,
- .cf_cpwait = cpufunc_nullop,
-
- /* MMU functions */
-
- .cf_control = (void *)cpufunc_nullop,
-
- /* TLB functions */
-
- .cf_tlb_flushID = cpufunc_nullop,
- .cf_tlb_flushID_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushI = cpufunc_nullop,
- .cf_tlb_flushI_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushD = cpufunc_nullop,
- .cf_tlb_flushD_SE = (void *)cpufunc_nullop,
-
- /* Cache operations */
-
- .cf_icache_sync_all = cpufunc_nullop,
- .cf_icache_sync_range = (void *) cpufunc_nullop,
-
- .cf_dcache_wbinv_all = arm3_cache_flush,
- .cf_dcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_dcache_inv_range = (void *)cpufunc_nullop,
- .cf_dcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_sdcache_inv_range = (void *)cpufunc_nullop,
- .cf_sdcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_idcache_wbinv_all = cpufunc_nullop,
- .cf_idcache_wbinv_range = (void *)cpufunc_nullop,
-
- /* Other functions */
-
- .cf_flush_prefetchbuf = cpufunc_nullop,
- .cf_drain_writebuf = cpufunc_nullop,
- .cf_flush_brnchtgt_C = cpufunc_nullop,
- .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
-
- .cf_sleep = (void *)cpufunc_nullop,
-
- /* Soft functions */
-
- .cf_dataabt_fixup = early_abort_fixup,
- .cf_prefetchabt_fixup = cpufunc_null_fixup,
-
- .cf_setup = (void *)cpufunc_nullop
-
-};
-#endif /* CPU_ARM250 */
-
-#ifdef CPU_ARM3
-struct cpu_functions arm3_cpufuncs = {
- /* CPU functions */
-
- .cf_id = cpufunc_id,
- .cf_cpwait = cpufunc_nullop,
-
- /* MMU functions */
-
- .cf_control = arm3_control,
-
- /* TLB functions */
-
- .cf_tlb_flushID = cpufunc_nullop,
- .cf_tlb_flushID_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushI = cpufunc_nullop,
- .cf_tlb_flushI_SE = (void *)cpufunc_nullop,
- .cf_tlb_flushD = cpufunc_nullop,
- .cf_tlb_flushD_SE = (void *)cpufunc_nullop,
-
- /* Cache operations */
-
- .cf_icache_sync_all = cpufunc_nullop,
- .cf_icache_sync_range = (void *) cpufunc_nullop,
-
- .cf_dcache_wbinv_all = arm3_cache_flush,
- .cf_dcache_wbinv_range = (void *)arm3_cache_flush,
- .cf_dcache_inv_range = (void *)arm3_cache_flush,
- .cf_dcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_sdcache_inv_range = (void *)cpufunc_nullop,
- .cf_sdcache_wb_range = (void *)cpufunc_nullop,
-
- .cf_idcache_wbinv_all = arm3_cache_flush,
- .cf_idcache_wbinv_range = (void *)arm3_cache_flush,
-
- /* Other functions */
-
- .cf_flush_prefetchbuf = cpufunc_nullop,
- .cf_drain_writebuf = cpufunc_nullop,
- .cf_flush_brnchtgt_C = cpufunc_nullop,
- .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
-
- .cf_sleep = (void *)cpufunc_nullop,
-
- /* Soft functions */
-
- .cf_dataabt_fixup = early_abort_fixup,
- .cf_prefetchabt_fixup = cpufunc_null_fixup,
-
- .cf_setup = (void *)cpufunc_nullop
-
-};
-#endif /* CPU_ARM3 */
-
#ifdef CPU_ARM6
struct cpu_functions arm6_cpufuncs = {
/* CPU functions */
@@ -1684,8 +1516,7 @@ get_cachetype_cp15(void)
}
#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
-#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \
- defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_SA110) || \
+#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_SA110) || \
defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
/* Cache information for CPUs without cache type registers. */
struct cachetab {
@@ -1755,7 +1586,7 @@ get_cachetype_table(void)
arm_dcache_align_mask = arm_dcache_align - 1;
}
-#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA1111 || IXP12X0 */
+#endif /* ARM6 || ARM7 || SA110 || SA1100 || SA1111 || IXP12X0 */
#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
@@ -1793,28 +1624,6 @@ set_cpufuncs(void)
* NOTE: cpu_do_powersave defaults to off. If we encounter a
* CPU type where we want to use it by default, then we set it.
*/
-#ifdef CPU_ARM2
- if (cputype == CPU_ID_ARM2) {
- cpufuncs = arm2_cpufuncs;
- get_cachetype_table();
- return 0;
- }
-#endif /* CPU_ARM2 */
-#ifdef CPU_ARM250
- if (cputype == CPU_ID_ARM250) {
- cpufuncs = arm250_cpufuncs;
- get_cachetype_table();
- return 0;
- }
-#endif
-#ifdef CPU_ARM3
- if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
- (cputype & 0x00000f00) == 0x00000300) {
- cpufuncs = arm3_cpufuncs;
- get_cachetype_table();
- return 0;
- }
-#endif /* CPU_ARM3 */
#ifdef CPU_ARM6
if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
(cputype & 0x00000f00) == 0x00000600) {
@@ -2179,22 +1988,6 @@ set_cpufuncs(void)
return ARCHITECTURE_NOT_PRESENT;
}
-#ifdef CPU_ARM2
-u_int arm2_id(void)
-{
-
- return CPU_ID_ARM2;
-}
-#endif /* CPU_ARM2 */
-
-#ifdef CPU_ARM250
-u_int arm250_id(void)
-{
-
- return CPU_ID_ARM250;
-}
-#endif /* CPU_ARM250 */
-
/*
* Fixup routines for data and prefetch aborts.
*
@@ -2218,8 +2011,7 @@ cpufunc_null_fixup(void *arg)
}
-#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \
- defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
+#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
#ifdef DEBUG_FAULT_CORRECTION
#define DFC_PRINTF(x) printf x
@@ -2364,7 +2156,7 @@ early_abort_fixup(void *arg)
return(ABORT_FIXUP_OK);
}
-#endif /* CPU_ARM2/250/3/6/7 */
+#endif /* CPU_ARM6/7 */
#if (defined(CPU_ARM6) && defined(ARM6_LATE_ABORT)) || defined(CPU_ARM7) || \
Index: src/sys/arch/arm/arm/fiq_subr.S
diff -u src/sys/arch/arm/arm/fiq_subr.S:1.7 src/sys/arch/arm/arm/fiq_subr.S:1.8
--- src/sys/arch/arm/arm/fiq_subr.S:1.7 Wed Jan 24 09:04:44 2018
+++ src/sys/arch/arm/arm/fiq_subr.S Fri Aug 10 16:17:29 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: fiq_subr.S,v 1.7 2018/01/24 09:04:44 skrll Exp $ */
+/* $NetBSD: fiq_subr.S,v 1.8 2018/08/10 16:17:29 maxv Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -41,16 +41,6 @@
#include <arm/asm.h>
#include <arm/cpuconf.h>
-/*
- * MODE_CHANGE_NOP should be inserted between a mode change and a
- * banked register (R8--R15) access.
- */
-#if defined(CPU_ARM2) || defined(CPU_ARM250)
-#define MODE_CHANGE_NOP mov r0, r0
-#else
-#define MODE_CHANGE_NOP /* Data sheet says ARM3 doesn't need it */
-#endif
-
#ifdef _ARM_ARCH_6
#define SWITCH_TO_FIQ_MODE \
cps #PSR_FIQ32_MODE
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.116 src/sys/arch/arm/arm32/cpu.c:1.117
--- src/sys/arch/arm/arm32/cpu.c:1.116 Sat Sep 16 00:47:16 2017
+++ src/sys/arch/arm/arm32/cpu.c Fri Aug 10 16:17:30 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.116 2017/09/16 00:47:16 matt Exp $ */
+/* $NetBSD: cpu.c,v 1.117 2018/08/10 16:17:30 maxv Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.116 2017/09/16 00:47:16 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.117 2018/08/10 16:17:30 maxv Exp $");
#include <sys/systm.h>
#include <sys/conf.h>
@@ -739,15 +739,6 @@ identify_arm_cpu(device_t dv, struct cpu
switch (cpu_class) {
-#ifdef CPU_ARM2
- case CPU_CLASS_ARM2:
-#endif
-#ifdef CPU_ARM250
- case CPU_CLASS_ARM2AS:
-#endif
-#ifdef CPU_ARM3
- case CPU_CLASS_ARM3:
-#endif
#ifdef CPU_ARM6
case CPU_CLASS_ARM6:
#endif
Index: src/sys/arch/arm/arm32/fault.c
diff -u src/sys/arch/arm/arm32/fault.c:1.106 src/sys/arch/arm/arm32/fault.c:1.107
--- src/sys/arch/arm/arm32/fault.c:1.106 Sun Jul 15 05:16:41 2018
+++ src/sys/arch/arm/arm32/fault.c Fri Aug 10 16:17:30 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: fault.c,v 1.106 2018/07/15 05:16:41 maxv Exp $ */
+/* $NetBSD: fault.c,v 1.107 2018/08/10 16:17:30 maxv Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -81,7 +81,7 @@
#include "opt_kgdb.h"
#include <sys/types.h>
-__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.106 2018/07/15 05:16:41 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.107 2018/08/10 16:17:30 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -119,8 +119,7 @@ extern char fusubailout[];
int last_fault_code; /* For the benefit of pmap_fault_fixup() */
#endif
-#if defined(CPU_ARM3) || defined(CPU_ARM6) || \
- defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
+#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
/* These CPUs may need data/prefetch abort fixups */
#define CPU_ABORT_FIXUP_REQUIRED
#endif
Index: src/sys/arch/arm/conf/files.arm
diff -u src/sys/arch/arm/conf/files.arm:1.139 src/sys/arch/arm/conf/files.arm:1.140
--- src/sys/arch/arm/conf/files.arm:1.139 Sun Apr 1 04:35:04 2018
+++ src/sys/arch/arm/conf/files.arm Fri Aug 10 16:17:30 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.139 2018/04/01 04:35:04 ryo Exp $
+# $NetBSD: files.arm,v 1.140 2018/08/10 16:17:30 maxv Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -17,9 +17,6 @@ defflag opt_cputypes.h CPU_ARMV5TE: CPU
defflag opt_cputypes.h CPU_XSCALE: CPU_ARMV5TE
defflag opt_cputypes.h CPU_ARMV6: ARM32_DISABLE_ALIGNMENT_FAULTS
defflag opt_cputypes.h CPU_ARMV7: ARM32_DISABLE_ALIGNMENT_FAULTS
-defflag opt_cputypes.h CPU_ARM2: CPU_ARMV2
-defflag opt_cputypes.h CPU_ARM250: CPU_ARMV2
-defflag opt_cputypes.h CPU_ARM3: CPU_ARMV2
defflag opt_cputypes.h CPU_ARM6: CPU_ARMV3
defflag opt_cputypes.h CPU_ARM7: CPU_ARMV3
defflag opt_cputypes.h CPU_ARM8: CPU_ARMV4
@@ -156,7 +153,6 @@ file arch/arm/arm/core_machdep.c
file arch/arm/arm/cpu_in_cksum.S (inet | inet6) & cpu_in_cksum
file arch/arm/arm/cpufunc.c
file arch/arm/arm/cpufunc_asm.S
-file arch/arm/arm/cpufunc_asm_arm3.S cpu_arm2 | cpu_arm250 | cpu_arm3
file arch/arm/arm/cpufunc_asm_arm67.S cpu_arm6 | cpu_arm7
file arch/arm/arm/cpufunc_asm_arm7tdmi.S cpu_arm7tdmi
file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8
Index: src/sys/arch/arm/include/cpuconf.h
diff -u src/sys/arch/arm/include/cpuconf.h:1.26 src/sys/arch/arm/include/cpuconf.h:1.27
--- src/sys/arch/arm/include/cpuconf.h:1.26 Sun Apr 1 04:35:04 2018
+++ src/sys/arch/arm/include/cpuconf.h Fri Aug 10 16:17:30 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuconf.h,v 1.26 2018/04/01 04:35:04 ryo Exp $ */
+/* $NetBSD: cpuconf.h,v 1.27 2018/08/10 16:17:30 maxv Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -62,9 +62,7 @@
* Step 1: Count the number of CPU types configured into the kernel.
*/
#if defined(_KERNEL_OPT)
-#define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \
- defined(CPU_ARM3) + \
- defined(CPU_ARM6) + defined(CPU_ARM7) + \
+#define CPU_NTYPES (defined(CPU_ARM6) + defined(CPU_ARM7) + \
defined(CPU_ARM7TDMI) + \
defined(CPU_ARM8) + defined(CPU_ARM9) + \
defined(CPU_ARM9E) + \
@@ -90,8 +88,7 @@
/*
* Step 2: Determine which ARM architecture versions are configured.
*/
-#if !defined(_KERNEL_OPT) || \
- (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
+#if !defined(_KERNEL_OPT)
#define ARM_ARCH_2 1
#else
#define ARM_ARCH_2 0
@@ -175,8 +172,7 @@
*
* ARM_MMU_V7 ARM v7 MMU.
*/
-#if !defined(_KERNEL_OPT) || \
- (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
+#if !defined(_KERNEL_OPT)
#define ARM_MMU_MEMC 1
#else
#define ARM_MMU_MEMC 0
Index: src/sys/arch/arm/include/cpufunc_proto.h
diff -u src/sys/arch/arm/include/cpufunc_proto.h:1.7 src/sys/arch/arm/include/cpufunc_proto.h:1.8
--- src/sys/arch/arm/include/cpufunc_proto.h:1.7 Fri Aug 25 17:43:33 2017
+++ src/sys/arch/arm/include/cpufunc_proto.h Fri Aug 10 16:17:30 2018
@@ -52,22 +52,6 @@
#include <arm/armreg.h>
#include <arm/cpuconf.h>
-#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
-void arm3_cache_flush (void);
-#endif /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
-
-#ifdef CPU_ARM2
-u_int arm2_id (void);
-#endif /* CPU_ARM2 */
-
-#ifdef CPU_ARM250
-u_int arm250_id (void);
-#endif
-
-#ifdef CPU_ARM3
-u_int arm3_control (u_int, u_int);
-#endif /* CPU_ARM3 */
-
#if defined(CPU_ARM6) || defined(CPU_ARM7)
void arm67_setttb (u_int, bool);
void arm67_tlb_flush (void);
