Module Name: src
Committed By: jmcneill
Date: Mon Oct 15 23:50:49 UTC 2018
Modified Files:
src/sys/arch/evbarm/conf: GENERIC64 VIRT
src/sys/conf: files
src/sys/dev/fdt: files.fdt pl061gpio_fdt.c
Added Files:
src/sys/dev/ic: pl061.c pl061var.h
Log Message:
Rename pl061gpio to plgpio and split the device logic from the FDT glue.
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/evbarm/conf/GENERIC64
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/evbarm/conf/VIRT
cvs rdiff -u -r1.1213 -r1.1214 src/sys/conf/files
cvs rdiff -u -r1.39 -r1.40 src/sys/dev/fdt/files.fdt
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/fdt/pl061gpio_fdt.c
cvs rdiff -u -r0 -r1.1 src/sys/dev/ic/pl061.c src/sys/dev/ic/pl061var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/conf/GENERIC64
diff -u src/sys/arch/evbarm/conf/GENERIC64:1.47 src/sys/arch/evbarm/conf/GENERIC64:1.48
--- src/sys/arch/evbarm/conf/GENERIC64:1.47 Mon Oct 15 11:35:42 2018
+++ src/sys/arch/evbarm/conf/GENERIC64 Mon Oct 15 23:50:48 2018
@@ -1,5 +1,5 @@
#
-# $NetBSD: GENERIC64,v 1.47 2018/10/15 11:35:42 jmcneill Exp $
+# $NetBSD: GENERIC64,v 1.48 2018/10/15 23:50:48 jmcneill Exp $
#
# GENERIC ARM (aarch64) kernel
#
@@ -182,7 +182,7 @@ tegra210car* at fdt? pass 3 # NVIDIA Te
# GPIO controller
bcmgpio* at fdt? # Broadcom BCM283x GPIO
-pl061gpio* at fdt? # ARM PrimeCell PL061 GPIO
+plgpio* at fdt? # ARM PrimeCell PL061 GPIO
sunxigpio* at fdt? pass 3 # Allwinner GPIO
tegragpio* at fdt? pass 2 # NVIDIA Tegra GPIO
rkgpio* at rkiomux? # Rockchip GPIO
Index: src/sys/arch/evbarm/conf/VIRT
diff -u src/sys/arch/evbarm/conf/VIRT:1.7 src/sys/arch/evbarm/conf/VIRT:1.8
--- src/sys/arch/evbarm/conf/VIRT:1.7 Sat Jul 14 15:09:41 2018
+++ src/sys/arch/evbarm/conf/VIRT Mon Oct 15 23:50:48 2018
@@ -1,5 +1,5 @@
#
-# $NetBSD: VIRT,v 1.7 2018/07/14 15:09:41 maxv Exp $
+# $NetBSD: VIRT,v 1.8 2018/10/15 23:50:48 jmcneill Exp $
#
# QEMU ARM 'virt' virtual machine
#
@@ -58,7 +58,7 @@ plcom* at fdt? # ARM PL011 UART
plrtc* at fdt? # ARM PrimeCell RTC
# GPIO
-pl061gpio* at fdt? # ARM PrimeCell GPIO
+plgpio* at fdt? # ARM PrimeCell GPIO
# Virtio devices
virtio* at fdt? # Virtio MMIO device
Index: src/sys/conf/files
diff -u src/sys/conf/files:1.1213 src/sys/conf/files:1.1214
--- src/sys/conf/files:1.1213 Sun Sep 23 09:21:03 2018
+++ src/sys/conf/files Mon Oct 15 23:50:48 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files,v 1.1213 2018/09/23 09:21:03 maxv Exp $
+# $NetBSD: files,v 1.1214 2018/10/15 23:50:48 jmcneill Exp $
# @(#)files.newconf 7.5 (Berkeley) 5/10/93
version 20171118
@@ -1319,6 +1319,10 @@ file dev/ic/pl041.c aaci
device plkmi: pckbport
file dev/ic/pl050.c plkmi
+# ARM PrimeCell PL061 (GPIO) general purpose input/output
+device plgpio: gpiobus
+file dev/ic/pl061.c plgpio
+
# ARM PrimeCell PL181 (MMCI) host controller
device plmmc: sdmmcbus
file dev/ic/pl181.c plmmc
Index: src/sys/dev/fdt/files.fdt
diff -u src/sys/dev/fdt/files.fdt:1.39 src/sys/dev/fdt/files.fdt:1.40
--- src/sys/dev/fdt/files.fdt:1.39 Sat Oct 6 16:28:21 2018
+++ src/sys/dev/fdt/files.fdt Mon Oct 15 23:50:48 2018
@@ -1,4 +1,4 @@
-# $NetBSD: files.fdt,v 1.39 2018/10/06 16:28:21 skrll Exp $
+# $NetBSD: files.fdt,v 1.40 2018/10/15 23:50:48 jmcneill Exp $
include "external/bsd/libfdt/conf/files.libfdt"
@@ -123,10 +123,9 @@ file dev/fdt/virtio_mmio_fdt.c virtio_m
attach qemufwcfg at fdt with qemufwcfg_fdt
file dev/fdt/qemufwcfg_fdt.c qemufwcfg_fdt
-# ARM PrimeCell General Purpose Input/Output (PL061)
-device pl061gpio: gpiobus
-attach pl061gpio at fdt with pl061gpio_fdt
-file dev/fdt/pl061gpio_fdt.c pl061gpio_fdt
+# ARM PrimeCell General Purpose Input/Output (PL061)
+attach plgpio at fdt with plgpio_fdt
+file dev/fdt/pl061gpio_fdt.c plgpio_fdt
# AHCI SATA controller
attach ahcisata at fdt with ahcisata_fdt
Index: src/sys/dev/fdt/pl061gpio_fdt.c
diff -u src/sys/dev/fdt/pl061gpio_fdt.c:1.2 src/sys/dev/fdt/pl061gpio_fdt.c:1.3
--- src/sys/dev/fdt/pl061gpio_fdt.c:1.2 Mon Sep 3 23:19:01 2018
+++ src/sys/dev/fdt/pl061gpio_fdt.c Mon Oct 15 23:50:48 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: pl061gpio_fdt.c,v 1.2 2018/09/03 23:19:01 jmcneill Exp $ */
+/* $NetBSD: pl061gpio_fdt.c,v 1.3 2018/10/15 23:50:48 jmcneill Exp $ */
/*
* Copyright (c) 2018 Jonathan A. Kollasch
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pl061gpio_fdt.c,v 1.2 2018/09/03 23:19:01 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl061gpio_fdt.c,v 1.3 2018/10/15 23:50:48 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -39,58 +39,40 @@ __KERNEL_RCSID(0, "$NetBSD: pl061gpio_fd
#include <sys/gpio.h>
#include <dev/gpio/gpiovar.h>
-#include "gpio.h"
#include <dev/ic/pl061reg.h>
+#include <dev/ic/pl061var.h>
#include <dev/fdt/fdtvar.h>
-static int pl061_gpio_match(device_t, cfdata_t, void *);
-static void pl061_gpio_attach(device_t, device_t, void *);
+static int plgpio_fdt_match(device_t, cfdata_t, void *);
+static void plgpio_fdt_attach(device_t, device_t, void *);
-static void * pl061_gpio_fdt_acquire(device_t, const void *,
+static void * plgpio_fdt_acquire(device_t, const void *,
size_t, int);
-static void pl061_gpio_fdt_release(device_t, void *);
-static int pl061_gpio_fdt_read(device_t, void *, bool);
-static void pl061_gpio_fdt_write(device_t, void *, int, bool);
-
-struct fdtbus_gpio_controller_func pl061_gpio_funcs = {
- .acquire = pl061_gpio_fdt_acquire,
- .release = pl061_gpio_fdt_release,
- .read = pl061_gpio_fdt_read,
- .write = pl061_gpio_fdt_write
+static void plgpio_fdt_release(device_t, void *);
+static int plgpio_fdt_read(device_t, void *, bool);
+static void plgpio_fdt_write(device_t, void *, int, bool);
+
+struct fdtbus_gpio_controller_func plgpio_fdt_funcs = {
+ .acquire = plgpio_fdt_acquire,
+ .release = plgpio_fdt_release,
+ .read = plgpio_fdt_read,
+ .write = plgpio_fdt_write
};
-struct pl061_gpio_softc {
- device_t sc_dev;
- bus_space_tag_t sc_bst;
- bus_space_handle_t sc_bsh;
-
- struct gpio_chipset_tag sc_gc;
- gpio_pin_t sc_pins[8];
-};
-
-struct pl061_gpio_pin {
- struct pl061_gpio_softc *pin_sc;
+struct plgpio_fdt_pin {
+ struct plgpio_softc * pin_sc;
int pin_no;
u_int pin_flags;
bool pin_actlo;
};
-static int pl061_gpio_pin_read(void *, int);
-static void pl061_gpio_pin_write(void *, int, int);
-static void pl061_gpio_pin_ctl(void *, int, int);
-
-CFATTACH_DECL_NEW(pl061gpio_fdt, sizeof(struct pl061_gpio_softc),
- pl061_gpio_match, pl061_gpio_attach, NULL, NULL);
-
-#define PL061_WRITE(sc, reg, val) \
- bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg)/4, (val))
-#define PL061_READ(sc, reg) \
- bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)/4)
+CFATTACH_DECL_NEW(plgpio_fdt, sizeof(struct plgpio_softc),
+ plgpio_fdt_match, plgpio_fdt_attach, NULL, NULL);
static int
-pl061_gpio_match(device_t parent, cfdata_t cf, void *aux)
+plgpio_fdt_match(device_t parent, cfdata_t cf, void *aux)
{
const char * const compatible[] = {
"arm,pl061",
@@ -102,16 +84,13 @@ pl061_gpio_match(device_t parent, cfdata
}
static void
-pl061_gpio_attach(device_t parent, device_t self, void *aux)
+plgpio_fdt_attach(device_t parent, device_t self, void *aux)
{
- struct pl061_gpio_softc * const sc = device_private(self);
+ struct plgpio_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
bus_addr_t addr;
bus_size_t size;
int error;
- struct gpiobus_attach_args gba;
- u_int pin;
-
if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
aprint_error(": couldn't get registers\n");
@@ -129,80 +108,17 @@ pl061_gpio_attach(device_t parent, devic
aprint_naive("\n");
aprint_normal(": GPIO\n");
- sc->sc_gc.gp_cookie = sc;
- sc->sc_gc.gp_pin_read = pl061_gpio_pin_read;
- sc->sc_gc.gp_pin_write = pl061_gpio_pin_write;
- sc->sc_gc.gp_pin_ctl = pl061_gpio_pin_ctl;
-
- const uint32_t cnf = PL061_READ(sc, PL061_GPIOAFSEL_REG);
-
- for (pin = 0; pin < 8; pin++) {
- sc->sc_pins[pin].pin_num = pin;
- /* skip pins in hardware control mode */
- if ((cnf & __BIT(pin)) != 0)
- continue;
- sc->sc_pins[pin].pin_caps =
- GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
- GPIO_PIN_TRISTATE;
- sc->sc_pins[pin].pin_state =
- pl061_gpio_pin_read(sc, pin);
- }
-
- memset(&gba, 0, sizeof(gba));
- gba.gba_gc = &sc->sc_gc;
- gba.gba_pins = sc->sc_pins;
- gba.gba_npins = 8;
-
-#if NGPIO > 0
- (void)config_found_ia(sc->sc_dev, "gpiobus", &gba,
- gpiobus_print);
-#endif
+ plgpio_attach(sc);
fdtbus_register_gpio_controller(self, faa->faa_phandle,
- &pl061_gpio_funcs);
-
-}
-
-static int
-pl061_gpio_pin_read(void *priv, int pin)
-{
- struct pl061_gpio_softc * const sc = priv;
-
- const uint32_t v = PL061_READ(sc, PL061_GPIODATA_REG(1<<pin));
-
- return (v >> pin) & 1;
-}
-
-static void
-pl061_gpio_pin_write(void *priv, int pin, int val)
-{
- struct pl061_gpio_softc * const sc = priv;
-
- PL061_WRITE(sc, PL061_GPIODATA_REG(1 << pin), val << pin);
-}
-
-static void
-pl061_gpio_pin_ctl(void *priv, int pin, int flags)
-{
- struct pl061_gpio_softc * const sc = priv;
- uint32_t v;
-
- if (flags & GPIO_PIN_INPUT) {
- v = PL061_READ(sc, PL061_GPIODIR_REG);
- v &= ~(1 << pin);
- PL061_WRITE(sc, PL061_GPIODIR_REG, v);
- } else if (flags & GPIO_PIN_OUTPUT) {
- v = PL061_READ(sc, PL061_GPIODIR_REG);
- v |= (1 << pin);
- PL061_WRITE(sc, PL061_GPIODIR_REG, v);
- }
+ &plgpio_fdt_funcs);
}
static void *
-pl061_gpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags)
+plgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags)
{
- struct pl061_gpio_softc * const sc = device_private(dev);
- struct pl061_gpio_pin *gpin;
+ struct plgpio_softc * const sc = device_private(dev);
+ struct plgpio_fdt_pin *gpin;
const u_int *gpio = data;
if (len != 12)
@@ -214,9 +130,9 @@ pl061_gpio_fdt_acquire(device_t dev, con
if (pin > 8)
return NULL;
- const uint32_t cnf = PL061_READ(sc, PL061_GPIOAFSEL_REG);
+ const uint32_t cnf = PLGPIO_READ(sc, PL061_GPIOAFSEL_REG);
if ((cnf & __BIT(pin)) != 0)
- PL061_WRITE(sc, PL061_GPIOAFSEL_REG, cnf & ~__BIT(pin));
+ PLGPIO_WRITE(sc, PL061_GPIOAFSEL_REG, cnf & ~__BIT(pin));
gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
gpin->pin_sc = sc;
@@ -224,27 +140,27 @@ pl061_gpio_fdt_acquire(device_t dev, con
gpin->pin_flags = flags;
gpin->pin_actlo = actlo;
- pl061_gpio_pin_ctl(gpin->pin_sc, gpin->pin_no, gpin->pin_flags);
+ plgpio_pin_ctl(gpin->pin_sc, gpin->pin_no, gpin->pin_flags);
return gpin;
}
static void
-pl061_gpio_fdt_release(device_t dev, void *priv)
+plgpio_fdt_release(device_t dev, void *priv)
{
- struct pl061_gpio_pin * const gpin = priv;
+ struct plgpio_fdt_pin * const gpin = priv;
- pl061_gpio_pin_ctl(gpin->pin_sc, gpin->pin_no, GPIO_PIN_INPUT);
+ plgpio_pin_ctl(gpin->pin_sc, gpin->pin_no, GPIO_PIN_INPUT);
kmem_free(gpin, sizeof(*gpin));
}
static int
-pl061_gpio_fdt_read(device_t dev, void *priv, bool raw)
+plgpio_fdt_read(device_t dev, void *priv, bool raw)
{
- struct pl061_gpio_pin * const gpin = priv;
+ struct plgpio_fdt_pin * const gpin = priv;
int val;
- val = pl061_gpio_pin_read(gpin->pin_sc, gpin->pin_no);
+ val = plgpio_pin_read(gpin->pin_sc, gpin->pin_no);
if (!raw && gpin->pin_actlo)
val = !val;
@@ -253,12 +169,12 @@ pl061_gpio_fdt_read(device_t dev, void *
}
static void
-pl061_gpio_fdt_write(device_t dev, void *priv, int val, bool raw)
+plgpio_fdt_write(device_t dev, void *priv, int val, bool raw)
{
- struct pl061_gpio_pin * const gpin = priv;
+ struct plgpio_fdt_pin * const gpin = priv;
if (!raw && gpin->pin_actlo)
val = !val;
- pl061_gpio_pin_write(gpin->pin_sc, gpin->pin_no, val);
+ plgpio_pin_write(gpin->pin_sc, gpin->pin_no, val);
}
Added files:
Index: src/sys/dev/ic/pl061.c
diff -u /dev/null src/sys/dev/ic/pl061.c:1.1
--- /dev/null Mon Oct 15 23:50:49 2018
+++ src/sys/dev/ic/pl061.c Mon Oct 15 23:50:48 2018
@@ -0,0 +1,116 @@
+/* $NetBSD: pl061.c,v 1.1 2018/10/15 23:50:48 jmcneill Exp $ */
+
+/*
+ * Copyright (c) 2018 Jonathan A. Kollasch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pl061.c,v 1.1 2018/10/15 23:50:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <dev/gpio/gpiovar.h>
+#include "gpio.h"
+
+#include <dev/ic/pl061reg.h>
+#include <dev/ic/pl061var.h>
+
+void
+plgpio_attach(struct plgpio_softc *sc)
+{
+ struct gpiobus_attach_args gba;
+ u_int pin;
+
+ sc->sc_gc.gp_cookie = sc;
+ sc->sc_gc.gp_pin_read = plgpio_pin_read;
+ sc->sc_gc.gp_pin_write = plgpio_pin_write;
+ sc->sc_gc.gp_pin_ctl = plgpio_pin_ctl;
+
+ const uint32_t cnf = PLGPIO_READ(sc, PL061_GPIOAFSEL_REG);
+
+ for (pin = 0; pin < 8; pin++) {
+ sc->sc_pins[pin].pin_num = pin;
+ /* skip pins in hardware control mode */
+ if ((cnf & __BIT(pin)) != 0)
+ continue;
+ sc->sc_pins[pin].pin_caps =
+ GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
+ GPIO_PIN_TRISTATE;
+ sc->sc_pins[pin].pin_state =
+ plgpio_pin_read(sc, pin);
+ }
+
+ memset(&gba, 0, sizeof(gba));
+ gba.gba_gc = &sc->sc_gc;
+ gba.gba_pins = sc->sc_pins;
+ gba.gba_npins = 8;
+
+#if NGPIO > 0
+ (void)config_found_ia(sc->sc_dev, "gpiobus", &gba,
+ gpiobus_print);
+#endif
+}
+
+int
+plgpio_pin_read(void *priv, int pin)
+{
+ struct plgpio_softc * const sc = priv;
+
+ const uint32_t v = PLGPIO_READ(sc, PL061_GPIODATA_REG(1<<pin));
+
+ return (v >> pin) & 1;
+}
+
+void
+plgpio_pin_write(void *priv, int pin, int val)
+{
+ struct plgpio_softc * const sc = priv;
+
+ PLGPIO_WRITE(sc, PL061_GPIODATA_REG(1 << pin), val << pin);
+}
+
+void
+plgpio_pin_ctl(void *priv, int pin, int flags)
+{
+ struct plgpio_softc * const sc = priv;
+ uint32_t v;
+
+ if (flags & GPIO_PIN_INPUT) {
+ v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
+ v &= ~(1 << pin);
+ PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
+ } else if (flags & GPIO_PIN_OUTPUT) {
+ v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
+ v |= (1 << pin);
+ PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
+ }
+}
Index: src/sys/dev/ic/pl061var.h
diff -u /dev/null src/sys/dev/ic/pl061var.h:1.1
--- /dev/null Mon Oct 15 23:50:49 2018
+++ src/sys/dev/ic/pl061var.h Mon Oct 15 23:50:48 2018
@@ -0,0 +1,52 @@
+/* $NetBSD: pl061var.h,v 1.1 2018/10/15 23:50:48 jmcneill Exp $ */
+
+/*
+ * Copyright (c) 2018 Jonathan A. Kollasch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PL061VAR_H
+#define _PL061VAR_H
+
+struct plgpio_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+
+ struct gpio_chipset_tag sc_gc;
+ gpio_pin_t sc_pins[8];
+};
+
+void plgpio_attach(struct plgpio_softc *);
+
+int plgpio_pin_read(void *, int);
+void plgpio_pin_write(void *, int, int);
+void plgpio_pin_ctl(void *, int, int);
+
+#define PLGPIO_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define PLGPIO_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+
+#endif /* !_PL061VAR_H */
