Module Name: src
Committed By: msaitoh
Date: Wed Nov 21 12:18:53 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.133 -r1.134 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.133 src/sys/arch/x86/include/specialreg.h:1.134
--- src/sys/arch/x86/include/specialreg.h:1.133 Wed Nov 21 06:09:49 2018
+++ src/sys/arch/x86/include/specialreg.h Wed Nov 21 12:18:53 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.133 2018/11/21 06:09:49 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.134 2018/11/21 12:18:53 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -415,6 +415,23 @@
"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD"
/*
+ * Intel CPUID Extended Topology Enumeration Fn0000000b
+ * %ecx == level number
+ * %eax: See below.
+ * %ebx: Number of logical processors at this level.
+ * %ecx: See below.
+ * %edx: x2APIC ID of the current logical processor.
+ */
+/* %eax */
+#define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */
+/* %ecx */
+#define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */
+#define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */
+#define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */
+#define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */
+#define CPUID_TOP_LVLTYPE_CORE 2 /* Core */
+
+/*
* Intel/AMD CPUID Processor extended state Enumeration Fn0000000d
*
* %ecx == 0: supported features info:
