Module Name: src
Committed By: skrll
Date: Sat Nov 24 15:40:57 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic_reg.h gicv3_its.c
Log Message:
Handle ThunderX errata
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_reg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_reg.h
diff -u src/sys/arch/arm/cortex/gic_reg.h:1.9 src/sys/arch/arm/cortex/gic_reg.h:1.10
--- src/sys/arch/arm/cortex/gic_reg.h:1.9 Tue Nov 13 22:25:28 2018
+++ src/sys/arch/arm/cortex/gic_reg.h Sat Nov 24 15:40:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_reg.h,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */
+/* $NetBSD: gic_reg.h,v 1.10 2018/11/24 15:40:57 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -335,6 +335,11 @@
#define GITS_CTLR_ImDe __BIT(1)
#define GITS_CTLR_Enabled __BIT(0)
+#define GITS_IIDR_ProductID __BITS(31,24)
+#define GITS_IIDR_Variant __BITS(19,16)
+#define GITS_IIDR_Revision __BITS(15,12)
+#define GITS_IIDR_Implementor __BITS(11,0)
+
#define GITS_TYPER_VMOVP __BIT(37)
#define GITS_TYPER_CIL __BIT(36)
#define GITS_TYPER_CIDbits __BITS(35,32)
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.7 src/sys/arch/arm/cortex/gicv3_its.c:1.8
--- src/sys/arch/arm/cortex/gicv3_its.c:1.7 Fri Nov 23 16:01:27 2018
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Nov 24 15:40:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.7 2018/11/23 16:01:27 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.8 2018/11/24 15:40:57 skrll Exp $");
#include <sys/param.h>
#include <sys/kmem.h>
@@ -56,6 +56,13 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,
#define GITS_ITT_ALIGN 0x100
+/*
+ * IIDR values used for errata
+ */
+#define GITS_IIDR_PID_CAVIUM_THUNDERX 0xa1
+#define GITS_IIDR_IMP_CAVIUM 0x34c
+
+
static inline uint32_t
gits_read_4(struct gicv3_its *its, bus_size_t reg)
{
@@ -594,7 +601,26 @@ gicv3_its_table_init(struct gicv3_softc
int tab;
const uint64_t typer = gits_read_8(its, GITS_TYPER);
- const u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+
+ /* devbits and innercache defaults */
+ u_int devbits = __SHIFTOUT(typer, GITS_TYPER_Devbits) + 1;
+ u_int innercache = GITS_Cache_NORMAL_NC;
+
+ uint32_t iidr = gits_read_4(its, GITS_IIDR);
+ const uint32_t ctx =
+ __SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) |
+ __SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) |
+ __SHIFTIN(0, GITS_IIDR_Variant);
+ const uint32_t mask =
+ GITS_IIDR_Implementor |
+ GITS_IIDR_ProductID |
+ GITS_IIDR_Variant;
+
+ if ((iidr & mask) == ctx) {
+ devbits = 20; /* 8Mb */
+ innercache = GITS_Cache_DEVICE_nGnRnE;
+ aprint_normal_dev(sc->sc_dev, "Cavium ThunderX errata detected\n");
+ }
for (tab = 0; tab < 8; tab++) {
baser = gits_read_8(its, GITS_BASERn(tab));
@@ -646,11 +672,11 @@ gicv3_its_table_init(struct gicv3_softc
baser &= ~GITS_BASER_Physical_Address;
baser |= its->its_tab[tab].segs[0].ds_addr;
baser &= ~GITS_BASER_InnerCache;
- baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache);
+ baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache);
baser &= ~GITS_BASER_Shareability;
baser |= __SHIFTIN(GITS_Shareability_NS, GITS_BASER_Shareability);
baser |= GITS_BASER_Valid;
-
+
gits_write_8(its, GITS_BASERn(tab), baser);
}
}
