Module Name: src
Committed By: ryo
Date: Thu Dec 13 10:44:25 UTC 2018
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S db_machdep.c genassym.cf
locore.S process_machdep.c trap.c
src/sys/arch/aarch64/include: armreg.h ptrace.h
Log Message:
add support PT_STEP
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/db_machdep.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/genassym.cf
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/process_machdep.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.9 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.10
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.9 Wed Dec 12 11:14:51 2018
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.9 2018/12/12 11:14:51 ryo Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.10 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.9 2018/12/12 11:14:51 ryo Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.10 2018/12/13 10:44:25 ryo Exp $")
/*
* At IPL_SCHED:
@@ -341,6 +341,13 @@ ENTRY_NP(el0_trap_exit)
msr spsr_el1, x1 /* exception pstate */
msr sp_el0, x2 /* restore EL0 stack */
+ /* if the process is traced, enable MDSCR_EL1.SS */
+ tbz x1, #SPSR_SS_SHIFT, 1f
+ mrs x0, mdscr_el1
+ orr x0, x0, #MDSCR_SS
+ msr mdscr_el1, x0
+1:
+
unwind_x0_x2
/* leave sp at l_md.md_utf, return back to EL0 user process */
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.11 src/sys/arch/aarch64/aarch64/db_machdep.c:1.12
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.11 Wed Nov 28 19:13:15 2018
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.11 2018/11/28 19:13:15 ryo Exp $ */
+/* $NetBSD: db_machdep.c,v 1.12 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.11 2018/11/28 19:13:15 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.12 2018/12/13 10:44:25 ryo Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -616,11 +616,9 @@ db_machdep_init(void)
}
mdscr = reg_mdscr_el1_read();
- mdscr |= __BIT(15);
- mdscr |= __BIT(13);
+ mdscr |= MDSCR_MDE; /* enable watchpoint and breakpoint */
reg_mdscr_el1_write(mdscr);
reg_oslar_el1_write(0);
- daif_enable(DAIF_D);
}
static void
Index: src/sys/arch/aarch64/aarch64/genassym.cf
diff -u src/sys/arch/aarch64/aarch64/genassym.cf:1.10 src/sys/arch/aarch64/aarch64/genassym.cf:1.11
--- src/sys/arch/aarch64/aarch64/genassym.cf:1.10 Tue Dec 11 05:46:14 2018
+++ src/sys/arch/aarch64/aarch64/genassym.cf Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.10 2018/12/11 05:46:14 ryo Exp $
+# $NetBSD: genassym.cf,v 1.11 2018/12/13 10:44:25 ryo Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -329,6 +329,7 @@ define DAIF_SETCLR_SHIFT DAIF_SETCLR_SHI
define CNTHCTL_EL1PCTEN CNTHCTL_EL1PCTEN
define CNTHCTL_EL1PCEN CNTHCTL_EL1PCEN
define CNTKCTL_EL0VCTEN CNTKCTL_EL0VCTEN
+define SPSR_SS_SHIFT SPSR_SS_SHIFT
define SPSR_F SPSR_F
define SPSR_I SPSR_I
define SPSR_A SPSR_A
@@ -352,6 +353,11 @@ define MPIDR_AFF1 MPIDR_AFF1
define MPIDR_AFF2 MPIDR_AFF2
define MPIDR_AFF3 MPIDR_AFF3
+define MDSCR_MDE MDSCR_MDE
+define MDSCR_KDE MDSCR_KDE
+define MDSCR_TDCC MDSCR_TDCC
+define MDSCR_SS MDSCR_SS
+
define MAIR_ATTR0 MAIR_ATTR0
define MAIR_ATTR1 MAIR_ATTR1
define MAIR_ATTR2 MAIR_ATTR2
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.31 src/sys/arch/aarch64/aarch64/locore.S:1.32
--- src/sys/arch/aarch64/aarch64/locore.S:1.31 Thu Nov 8 08:28:07 2018
+++ src/sys/arch/aarch64/aarch64/locore.S Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.31 2018/11/08 08:28:07 maxv Exp $ */
+/* $NetBSD: locore.S,v 1.32 2018/12/13 10:44:25 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -39,7 +39,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.31 2018/11/08 08:28:07 maxv Exp $")
+RCSID("$NetBSD: locore.S,v 1.32 2018/12/13 10:44:25 ryo Exp $")
/*#define DEBUG_LOCORE /* debug print */
@@ -218,8 +218,10 @@ ASEND(clear_bss)
init_sysregs:
stp x0, lr, [sp, #-16]!
- /* Disable debug event */
- msr mdscr_el1, xzr
+ /* init debug event */
+ ldr x0, mdscr_setting
+ msr mdscr_el1, x0
+ msr oslar_el1, xzr
/* Clear context id register */
msr contextidr_el1, xzr
@@ -1008,6 +1010,11 @@ sctlr_clear:
SCTLR_A | /* Alignment check enable */ \
0)
+mdscr_setting:
+ .quad ( \
+ MDSCR_TDCC | /* Trap Debug Communications Channel access */ \
+ 0)
+
.L_devmap_addr:
.quad VM_KERNEL_IO_ADDRESS
Index: src/sys/arch/aarch64/aarch64/process_machdep.c
diff -u src/sys/arch/aarch64/aarch64/process_machdep.c:1.3 src/sys/arch/aarch64/aarch64/process_machdep.c:1.4
--- src/sys/arch/aarch64/aarch64/process_machdep.c:1.3 Tue Jul 17 00:36:30 2018
+++ src/sys/arch/aarch64/aarch64/process_machdep.c Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: process_machdep.c,v 1.3 2018/07/17 00:36:30 christos Exp $ */
+/* $NetBSD: process_machdep.c,v 1.4 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: process_machdep.c,v 1.3 2018/07/17 00:36:30 christos Exp $");
+__KERNEL_RCSID(1, "$NetBSD: process_machdep.c,v 1.4 2018/12/13 10:44:25 ryo Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -89,6 +89,17 @@ process_write_fpregs(struct lwp *l, cons
}
int
+process_sstep(struct lwp *l, int sstep)
+{
+ if (sstep)
+ l->l_md.md_utf->tf_spsr |= SPSR_SS;
+ else
+ l->l_md.md_utf->tf_spsr &= ~SPSR_SS;
+
+ return 0;
+}
+
+int
process_set_pc(struct lwp *l, void *addr)
{
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.13 src/sys/arch/aarch64/aarch64/trap.c:1.14
--- src/sys/arch/aarch64/aarch64/trap.c:1.13 Wed Dec 12 18:11:00 2018
+++ src/sys/arch/aarch64/aarch64/trap.c Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.13 2018/12/12 18:11:00 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.14 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.13 2018/12/12 18:11:00 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.14 2018/12/13 10:44:25 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -232,6 +232,8 @@ trap_el0_sync(struct trapframe *tf)
const uint32_t esr = tf->tf_esr;
const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */
+ /* disable trace */
+ reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
/* enable traps and interrupts */
daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F);
@@ -265,11 +267,16 @@ trap_el0_sync(struct trapframe *tf)
case ESR_EC_BKPT_INSN_A64:
case ESR_EC_BRKPNT_EL0:
- case ESR_EC_SW_STEP_EL0:
case ESR_EC_WTCHPNT_EL0:
do_trapsignal(l, SIGTRAP, TRAP_BRKPT, (void *)tf->tf_pc, esr);
userret(l);
break;
+ case ESR_EC_SW_STEP_EL0:
+ /* disable trace, and send trace trap */
+ tf->tf_spsr &= ~SPSR_SS;
+ do_trapsignal(l, SIGTRAP, TRAP_TRACE, (void *)tf->tf_pc, esr);
+ userret(l);
+ break;
default:
case ESR_EC_UNKNOWN:
@@ -305,6 +312,9 @@ interrupt(struct trapframe *tf)
}
#endif
+ /* disable trace */
+ reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
+
/* enable traps */
daif_enable(DAIF_D|DAIF_A);
@@ -322,6 +332,8 @@ trap_el0_32sync(struct trapframe *tf)
const uint32_t esr = tf->tf_esr;
const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */
+ /* disable trace */
+ reg_mdscr_el1_write(reg_mdscr_el1_read() & ~MDSCR_SS);
/* enable traps and interrupts */
daif_enable(DAIF_D|DAIF_A|DAIF_I|DAIF_F);
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.21 src/sys/arch/aarch64/include/armreg.h:1.22
--- src/sys/arch/aarch64/include/armreg.h:1.21 Tue Nov 20 01:59:51 2018
+++ src/sys/arch/aarch64/include/armreg.h Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.21 2018/11/20 01:59:51 mrg Exp $ */
+/* $NetBSD: armreg.h,v 1.22 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -596,6 +596,7 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
#define SPSR_A32_IT1 __BIT(23) // A32: IT[1]
#define SPSR_A32_IT0 __BIT(22) // A32: IT[0]
#define SPSR_SS __BIT(21) // Software Step
+#define SPSR_SS_SHIFT 21
#define SPSR_IL __BIT(20) // Instruction Length
#define SPSR_GE __BITS(19,16) // A32: SIMD GE
#define SPSR_IT7 __BIT(15) // A32: IT[7]
@@ -805,6 +806,19 @@ AARCH64REG_WRITE_INLINE(dbgwvr15_el1)
AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register
AARCH64REG_WRITE_INLINE(mdscr_el1)
+#define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull
+#define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull
+#define MDSCR_RXO __BIT(27) // for EDSCR.RXO
+#define MDSCR_TXU __BIT(26) // for EDSCR.TXU
+#define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis
+#define MDSCR_TDA __BIT(21) // for EDSCR.TDA
+#define MDSCR_MDE __BIT(15) // Monitor debug events
+#define MDSCR_HDE __BIT(14) // for EDSCR.HDE
+#define MDSCR_KDE __BIT(13) // Local debug enable
+#define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access
+#define MDSCR_ERR __BIT(6) // for EDSCR.ERR
+#define MDSCR_SS __BIT(0) // Software step
+
AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register
AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register
Index: src/sys/arch/aarch64/include/ptrace.h
diff -u src/sys/arch/aarch64/include/ptrace.h:1.7 src/sys/arch/aarch64/include/ptrace.h:1.8
--- src/sys/arch/aarch64/include/ptrace.h:1.7 Sat Jul 21 18:58:05 2018
+++ src/sys/arch/aarch64/include/ptrace.h Thu Dec 13 10:44:25 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.7 2018/07/21 18:58:05 ryo Exp $ */
+/* $NetBSD: ptrace.h,v 1.8 2018/12/13 10:44:25 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,18 +36,23 @@
/*
* AARCH64-dependent ptrace definitions.
- * Note that PT_STEP is _not_ supported.
*/
-#define PT_GETREGS (PT_FIRSTMACH + 0)
-#define PT_SETREGS (PT_FIRSTMACH + 1)
-#define PT_GETFPREGS (PT_FIRSTMACH + 2)
-#define PT_SETFPREGS (PT_FIRSTMACH + 3)
+#define PT_GETREGS (PT_FIRSTMACH + 0)
+#define PT_SETREGS (PT_FIRSTMACH + 1)
+#define PT_GETFPREGS (PT_FIRSTMACH + 2)
+#define PT_SETFPREGS (PT_FIRSTMACH + 3)
+#define PT_STEP (PT_FIRSTMACH + 4)
+#define PT_SETSTEP (PT_FIRSTMACH + 5)
+#define PT_CLEARSTEP (PT_FIRSTMACH + 6)
#define PT_MACHDEP_STRINGS \
"PT_GETREGS", \
"PT_SETREGS", \
"PT_GETFPREGS", \
- "PT_SETFPREGS",
+ "PT_SETFPREGS", \
+ "PT_STEP", \
+ "PT_SETSTEP", \
+ "PT_CLEARSTEP",
#include <machine/reg.h>
