Module Name: src
Committed By: msaitoh
Date: Fri Dec 28 06:20:32 UTC 2018
Modified Files:
src/sys/dev/mii: makphy.c makphyreg.h
Removed Files:
src/sys/dev/mii: e1000phyreg.h
Log Message:
- Backout some changes done in rev. 1.44. OK'd by jdolecek@:
- Remove e1000phyreg.h and use makphyreg.h again.
- Remove Energy detect stuff. Leave it by default.
- Remove MDI crossover configuraton. Leave it by default. I think it's OK to
add new API to change the mode.
- PHY_RESET() is used to commit some changes, so I think it's not good to
always clear BMCR_AUTOEN before reset in makphy_reset().
- It's not required to read MII_100T2SR twice because this register has no
any bit which is latched.
- Use mii_phy_reset() instead of extracted code.
- Don't set PSCR_CRS_ON_TX on newer. Those chips have no this bit.
- Add some "XXX FIXME" comment. Non GMII mode uses different page except
very old chip. Some bits are at the same location but others are not.
- Remove obsolete comment.
- s/MII_MAKPHY_/MAKPHY_/
XXX rev. 1.44 changed the setting of mii_media_active when the interface is
set to other than auto. I suspect the intention of the change is to reflect
the link up/down status. But, it didn't work because non auto setting makes
PSSR_LINK bit alwasy set "without modifing some registers".
This commit won't fix the change and it'll be fixed in the next commit.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r0 src/sys/dev/mii/e1000phyreg.h
cvs rdiff -u -r1.45 -r1.46 src/sys/dev/mii/makphy.c
cvs rdiff -u -r1.8 -r1.9 src/sys/dev/mii/makphyreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/makphy.c
diff -u src/sys/dev/mii/makphy.c:1.45 src/sys/dev/mii/makphy.c:1.46
--- src/sys/dev/mii/makphy.c:1.45 Mon Jun 18 09:12:17 2018
+++ src/sys/dev/mii/makphy.c Fri Dec 28 06:20:32 2018
@@ -1,5 +1,4 @@
-/* $NetBSD: makphy.c,v 1.45 2018/06/18 09:12:17 msaitoh Exp $ */
-/* $OpenBSD: eephy.c,v 1.56 2015/03/14 03:38:48 jsg Exp $ */
+/* $NetBSD: makphy.c,v 1.46 2018/12/28 06:20:32 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -55,48 +54,8 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/*
- * Principal Author: Parag Patel
- * Copyright (c) 2001
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice unmodified, this list of conditions, and the following
- * disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * Additonal Copyright (c) 2001 by Traakan Software under same licence.
- * Secondary Author: Matthew Jacob
- */
-/*
- * Driver for the Marvell 88E1000 ``Alaska'' 10/100/1000 PHY.
- */
-
-/*
- * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
- * 1000baseSX PHY.
- * Nathan Binkert <n...@openbsd.org>
- */
-
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.45 2018/06/18 09:12:17 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.46 2018/12/28 06:20:32 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -112,7 +71,7 @@ __KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1
#include <dev/mii/miivar.h>
#include <dev/mii/miidevs.h>
-#include <dev/mii/e1000phyreg.h>
+#include <dev/mii/makphyreg.h>
static int makphymatch(device_t, cfdata_t, void *);
static void makphyattach(device_t, device_t, void *);
@@ -124,11 +83,11 @@ static int makphy_service(struct mii_sof
static void makphy_status(struct mii_softc *);
static void makphy_reset(struct mii_softc *);
-static const struct mii_phy_funcs eephy_funcs = {
+static const struct mii_phy_funcs makphy_funcs = {
makphy_service, makphy_status, makphy_reset,
};
-static const struct mii_phydesc eephys[] = {
+static const struct mii_phydesc makphys[] = {
{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_0,
MII_STR_MARVELL_E1000_0 },
@@ -174,7 +133,6 @@ static const struct mii_phydesc eephys[]
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1145,
MII_STR_xxMARVELL_E1145 },
- /* XXX: reported not to work on eg. HP XW9400 */
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1149,
MII_STR_xxMARVELL_E1149 },
@@ -192,6 +150,7 @@ static const struct mii_phydesc eephys[]
{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_PHYG65G,
MII_STR_xxMARVELL_PHYG65G },
+
{ 0, 0,
NULL },
};
@@ -201,7 +160,7 @@ makphymatch(device_t parent, cfdata_t ma
{
struct mii_attach_args *ma = aux;
- if (mii_phy_match(ma, eephys) != NULL)
+ if (mii_phy_match(ma, makphys) != NULL)
return (10);
return (0);
@@ -215,7 +174,7 @@ makphyattach(device_t parent, device_t s
struct mii_data *mii = ma->mii_data;
const struct mii_phydesc *mpd;
- mpd = mii_phy_match(ma, eephys);
+ mpd = mii_phy_match(ma, makphys);
aprint_naive(": Media interface\n");
aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
@@ -225,45 +184,22 @@ makphyattach(device_t parent, device_t s
sc->mii_mpd_rev = MII_REV(ma->mii_id2);
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
- sc->mii_funcs = &eephy_funcs;
+ sc->mii_funcs = &makphy_funcs;
sc->mii_pdata = mii;
sc->mii_flags = ma->mii_flags;
sc->mii_anegticks = MII_ANEGTICKS;
- /* XXX No loopback support yet, although the hardware can do it. */
- sc->mii_flags |= MIIF_NOLOOP;
-
/* Make sure page 0 is selected. */
- PHY_WRITE(sc, E1000_EADR, 0);
+ PHY_WRITE(sc, MAKPHY_EADR, 0);
- /* Switch to copper-only mode if necessary. */
- if (sc->mii_mpd_model == MII_MODEL_MARVELL_E1111 &&
- (sc->mii_flags & MIIF_HAVEFIBER) == 0) {
- /*
- * The onboard 88E1111 PHYs on the Sun X4100 M2 come
- * up with fiber/copper auto-selection enabled, even
- * though the machine only has copper ports. This
- * makes the chip autoselect to 1000baseX, and makes
- * it impossible to select any other media. So
- * disable fiber/copper autoselection.
- */
- int reg = PHY_READ(sc, E1000_ESSR);
- if ((reg & E1000_ESSR_HWCFG_MODE) == E1000_ESSR_RGMII_COPPER) {
- reg |= E1000_ESSR_DIS_FC;
- PHY_WRITE(sc, E1000_ESSR, reg);
- }
- }
-
- /* Switch to fiber-only mode if necessary. */
- if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112 &&
- sc->mii_flags & MIIF_HAVEFIBER) {
- int page = PHY_READ(sc, E1000_EADR);
- PHY_WRITE(sc, E1000_EADR, 2);
- int reg = PHY_READ(sc, E1000_SCR);
- reg &= ~E1000_SCR_MODE_MASK;
- reg |= E1000_SCR_MODE_1000BX;
- PHY_WRITE(sc, E1000_SCR, reg);
- PHY_WRITE(sc, E1000_EADR, page);
+ switch (sc->mii_mpd_model) {
+ case MII_MODEL_xxMARVELL_E1011:
+ case MII_MODEL_xxMARVELL_E1112:
+ if (PHY_READ(sc, MAKPHY_ESSR) & ESSR_FIBER_LINK)
+ sc->mii_flags |= MIIF_HAVEFIBER;
+ break;
+ default:
+ break;
}
PHY_RESET(sc);
@@ -284,72 +220,42 @@ makphyattach(device_t parent, device_t s
static void
makphy_reset(struct mii_softc *sc)
{
- int reg, i;
+ int reg;
- reg = PHY_READ(sc, MII_BMCR);
- reg |= BMCR_RESET;
- PHY_WRITE(sc, MII_BMCR, reg);
-
- for (i = 0; i < 500; i++) {
- DELAY(1);
- reg = PHY_READ(sc, MII_BMCR);
- if (!(reg & BMCR_RESET))
- break;
- }
+ mii_phy_reset(sc);
/*
* Initialize PHY Specific Control Register.
*/
- reg = PHY_READ(sc, E1000_SCR);
+ reg = PHY_READ(sc, MAKPHY_PSCR);
/* Assert CRS on transmit. */
- reg |= E1000_SCR_ASSERT_CRS_ON_TX;
-
- /* Enable auto crossover. */
switch (sc->mii_mpd_model) {
- case MII_MODEL_xxMARVELL_E3016:
- case MII_MODEL_xxMARVELL_E3082:
- /* Bits are in a different position. */
- reg |= (E1000_SCR_AUTO_X_MODE >> 1);
+ case MII_MODEL_MARVELL_E1000_0:
+ case MII_MODEL_MARVELL_E1000_3:
+ case MII_MODEL_MARVELL_E1000_5:
+ case MII_MODEL_MARVELL_E1000_6:
+ case MII_MODEL_xxMARVELL_E1000S:
+ case MII_MODEL_xxMARVELL_E1011:
+ case MII_MODEL_xxMARVELL_E1111:
+ reg |= PSCR_CRS_ON_TX;
break;
- default:
- /* Automatic crossover causes problems for 1000baseX. */
- if (sc->mii_flags & MIIF_IS_1000X)
- reg &= ~E1000_SCR_AUTO_X_MODE;
- else
- reg |= E1000_SCR_AUTO_X_MODE;
- }
-
- /* Disable energy detect; only available on some models. */
- switch(sc->mii_mpd_model) {
- case MII_MODEL_xxMARVELL_E3016:
- reg &= ~E3000_SCR_EN_DETECT_MASK;
- break;
- case MII_MODEL_MARVELL_E1011:
- case MII_MODEL_MARVELL_E1111:
- case MII_MODEL_xxMARVELL_E1112:
- case MII_MODEL_xxMARVELL_PHYG65G:
- reg &= ~E1000_SCR_EN_DETECT_MASK;
+ default: /* No PSCR_CRS_ON_TX bit */
break;
}
/* Enable scrambler if necessary. */
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
- reg &= ~E3000_SCR_SCRAMBLER_DISABLE;
+ reg &= ~E3016_PSCR_SCRAMBLE_DIS;
/*
* Store next page in the Link Partner Next Page register for
* compatibility with 802.3ab.
*/
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
- reg |= E3000_SCR_REG8_NEXT_PAGE;
-
- PHY_WRITE(sc, E1000_SCR, reg);
+ reg |= E3016_PSCR_REG8NXTPG;
- /* 25 MHz TX_CLK should always work. */
- reg = PHY_READ(sc, E1000_ESCR);
- reg |= E1000_ESCR_TX_CLK_25;
- PHY_WRITE(sc, E1000_ESCR, reg);
+ PHY_WRITE(sc, MAKPHY_PSCR, reg);
/* Configure LEDs if they were left unconfigured. */
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016 &&
@@ -358,14 +264,7 @@ makphy_reset(struct mii_softc *sc)
PHY_WRITE(sc, 0x16, reg);
}
- /*
- * Do a software reset for these settings to take effect.
- * Disable autonegotiation, such that all capabilities get
- * advertised when it is switched back on.
- */
- reg = PHY_READ(sc, MII_BMCR);
- reg &= ~BMCR_AUTOEN;
- PHY_WRITE(sc, MII_BMCR, reg | BMCR_RESET);
+ mii_phy_reset(sc);
}
static int
@@ -443,15 +342,16 @@ static void
makphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
- int bmcr, gsr, ssr;
+ int bmcr, gsr, pssr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmcr = PHY_READ(sc, MII_BMCR);
- ssr = PHY_READ(sc, E1000_SSR);
+ /* XXX FIXME: Use different page for Fiber on newer chips */
+ pssr = PHY_READ(sc, MAKPHY_PSSR);
- if (ssr & E1000_SSR_LINK)
+ if (pssr & PSSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
if (bmcr & BMCR_ISO) {
@@ -463,30 +363,44 @@ makphy_status(struct mii_softc *sc)
if (bmcr & BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
- if (!(ssr & E1000_SSR_SPD_DPLX_RESOLVED)) {
+ /*
+ * Check Speed and Duplex Resolved bit.
+ * XXX Note that this bit is always 1 when autonego is not enabled.
+ */
+ if (!(pssr & PSSR_RESOLVED)) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
+ /* XXX FIXME: Use different page for Fiber on newer chips */
if (sc->mii_flags & MIIF_IS_1000X) {
mii->mii_media_active |= IFM_1000_SX;
} else {
- if (ssr & E1000_SSR_1000MBS)
+ switch (PSSR_SPEED_get(pssr)) {
+ case SPEED_1000:
mii->mii_media_active |= IFM_1000_T;
- else if (ssr & E1000_SSR_100MBS)
+ break;
+ case SPEED_100:
mii->mii_media_active |= IFM_100_TX;
- else
+ break;
+ case SPEED_10:
mii->mii_media_active |= IFM_10_T;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ mii->mii_media_status = 0;
+ return;
+ }
}
- if (ssr & E1000_SSR_DUPLEX)
+ if (pssr & PSSR_DUPLEX)
mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
- gsr = PHY_READ(sc, MII_100T2SR) | PHY_READ(sc, MII_100T2SR);
+ gsr = PHY_READ(sc, MII_100T2SR);
if (gsr & GTSR_MS_RES)
mii->mii_media_active |= IFM_ETH_MASTER;
}
Index: src/sys/dev/mii/makphyreg.h
diff -u src/sys/dev/mii/makphyreg.h:1.8 src/sys/dev/mii/makphyreg.h:1.9
--- src/sys/dev/mii/makphyreg.h:1.8 Tue Dec 25 08:33:52 2018
+++ src/sys/dev/mii/makphyreg.h Fri Dec 28 06:20:32 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: makphyreg.h,v 1.8 2018/12/25 08:33:52 msaitoh Exp $ */
+/* $NetBSD: makphyreg.h,v 1.9 2018/12/28 06:20:32 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
* Marvell 88E1000 ``Alaska'' 10/100/1000 PHY registers.
*/
-#define MII_MAKPHY_PSCR 0x10 /* PHY specific control register */
+#define MAKPHY_PSCR 0x10 /* PHY specific control register */
#define PSCR_DIS_JABBER (1U << 0) /* disable jabber */
#define PSCR_POL_REV (1U << 1) /* polarity reversal */
#define PSCR_SQE_TEST (1U << 2) /* SQE test */
@@ -44,6 +44,7 @@
#define PSCR_DIS_125CLK (1U << 4) /* 125CLK low */
#define PSCR_MDI_XOVER_MODE(x) ((x) << 5) /* crossover mode */
#define PSCR_LOW_10T_THRESH (1U << 7) /* lower 10BASE-T Rx threshold */
+#define PSCR_EN_DETECT(x) ((x) << 8) /* Energy Detect */
#define PSCR_FORCE_LINK_GOOD (1U << 10) /* force link good */
#define PSCR_CRS_ON_TX (1U << 11) /* assert CRS on transmit */
#define PSCR_RX_FIFO(x) ((x) << 12) /* Rx FIFO depth */
@@ -53,7 +54,44 @@
#define XOVER_MODE_MDIX 1
#define XOVER_MODE_AUTO 2
-#define MII_MAKPHY_PSSR 0x11 /* PHY specific status register */
+/* 88E3016 */
+/* bit 2 and 3 are reserved */
+#define E3016_PSCR_MDI_XOVER_MODE(x) ((x) << 4) /* crossover mode */
+#define E3016_PSCR_SIGDET_POLARITY (1U << 6) /* 0: Active H, 1: Active L */
+#define E3016_PSCR_EXTDIST (1U << 7) /* Enable Extended Distance */
+#define E3016_PSCR_FEFI_DIS (1U << 8) /* Disable FEFI */
+#define E3016_PSCR_SCRAMBLE_DIS (1U << 9) /* Disable Scrambler */
+/* bit 10 is reserved */
+#define E3016_PSCR_NLPGEN_DIS (1U << 11) /* Disable Linkpulse Generation */
+#define E3016_PSCR_REG8NXTPG (1U << 12) /* En. Link Partner Next Page R */
+#define E3016_PSCR_NLPCHK_DIS (1U << 13) /* Disable NLP check */
+#define E3016_PSCR_EN_DETECT (1U << 14) /* Energy Detect */
+/* bit 15 is reserved */
+
+/* 88E1112 page 1 */
+#define MAKPHY_FSCR 0x10 /* Fiber specific control register */
+#define FSCR_XMITTER_DIS 0x0008 /* Transmitter Disable */
+
+/* 88E1112 page 2 */
+#define MAKPHY_MSCR 0x10 /* MAC specific control register */
+#define MSCR_TX_FIFODEPTH 0xc000 /* Transmi FIFO Depth */
+#define MSCR_RX_FIFODEPTH 0x3000 /* Receive FIFO Depth */
+#define MSCR_AUTOPREF_MASK 0x0c00 /* Autoselect preferred media mask */
+#define MSCR_AUTOPREF_NO 0x0000 /* No preference */
+#define MSCR_AUTOPREF_FIBER 0x0400 /* Preferred Fiber */
+#define MSCR_AUTOPREF_COPPER 0x0800 /* Preferred Copper */
+#define MSCR_MODE_MASK 0x0380 /* Mode select mask */
+#define MSCR_M_100FX 0x0000 /* 100BASE-FX */
+#define MSCR_M_COOPER_GBIC 0x0080 /* Copper GBIC */
+#define MSCR_M_AUTO_COPPER_SGMII 0x0100 /* Auto Copper/SGMII */
+#define MSCR_M_AUTO_COPPER_1000X 0x0180 /* Auto Copper/1000BASE-X */
+#define MSCR_M_COPPER 0x0280 /* Copper only */
+#define MSCR_M_SGMII 0x0300 /* SGMII only */
+#define MSCR_M_1000X 0x0380 /* 1000BASE-X only */
+#define MSCR_SGMII_PDOWN 0x0008 /* SGMII MAC Interface Power Down */
+#define MSCR_ENHANCED_SGMII 0x0004 /* Enhanced SGMII */
+
+#define MAKPHY_PSSR 0x11 /* PHY specific status register */
#define PSSR_JABBER (1U << 0) /* jabber indication */
#define PSSR_POLARITY (1U << 1) /* polarity indiciation */
#define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */
@@ -69,7 +107,7 @@
#define SPEED_1000 2
#define SPEED_reserved 3
-#define MII_MAKPHY_IE 0x12 /* Interrupt enable */
+#define MAKPHY_IE 0x12 /* Interrupt enable */
#define IE_JABBER (1U << 0) /* jabber indication */
#define IE_POL_CHANGED (1U << 1) /* polarity changed */
#define IE_MDI_XOVER_CHANGED (1U << 6) /* MDI/MDIX changed */
@@ -83,20 +121,20 @@
#define IE_SPEED_CHANGED (1U << 14) /* speed changed */
#define IE_ANEG_ERROR (1U << 15) /* autonegotiation error occurred */
-#define MII_MAKPHY_IS 0x13 /* Interrupt status */
+#define MAKPHY_IS 0x13 /* Interrupt status */
/* See Interrupt enable bits */
-#define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */
+#define MAKPHY_EPSC 0x14 /* extended PHY specific control */
#define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */
#define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */
#define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */
#define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */
-#define MII_MAKPHY_REC 0x15 /* receive error counter */
+#define MAKPHY_REC 0x15 /* receive error counter */
-#define MII_MAKPHY_EADR 0x16 /* extended address register */
+#define MAKPHY_EADR 0x16 /* extended address register */
-#define MII_MAKPHY_LEDCTRL 0x18 /* LED control */
+#define MAKPHY_LEDCTRL 0x18 /* LED control */
#define LEDCTRL_LED_TX (1U << 0) /* 1 = activ/link, 0 = xmit */
#define LEDCTRL_LED_RX (1U << 1) /* 1 = activ/link, 1 = recv */
#define LEDCTRL_LED_DUPLEX (1U << 2) /* 1 = duplex, 0 = dup/coll */
@@ -105,10 +143,21 @@
#define LEDCTRL_PULSE_STRCH(x) ((x) << 12)
#define LEDCTRL_DISABLE (1U << 15) /* disable LED */
-#define MII_MAKPHY_ESSR 0x1b /* Extended PHY specific status */
-#define ESSR_FIBER_LINK 0x2000
+#define MAKPHY_ESSR 0x1b /* Extended PHY specific status */
+#define ESSR_AUTOSEL_DISABLE 0x8000 /* Fiber/Copper autoselect disable */
+#define ESSR_FIBER_LINK 0x2000 /* Fiber/Copper resolution */
+#define ESSR_SER_ANEG_BYPASS 0x1000 /* Serial Iface Aneg bypass enable */
+#define ESSR_SER_ANEG_BYPASS_ST 0x0800 /* Serial Iface Aneg bypass status */
+#define ESSR_INTR_POLARITY 0x0400 /* Interrupt Polarity */
+#define ESSR_AUTO_MEDIAREG_SEL 0x0200 /* Auto Medium Register Selection */
+#define ESSR_DTE_DROP_HYST 0x01e0 /* DTE detect status drop hysteresis */
+#define ESSR_DTE_POWER 0x0010
+#define ESSR_HWCFG_MODE 0x000f
#define ESSR_GMII_COPPER 0x000f
#define ESSR_GMII_FIBER 0x0007
+#define ESSR_RGMII_COPPER 0x000b
+#define ESSR_RGMII_FIBER 0x0003
+#define ESSR_RGMII_SGMII 0x0006
#define ESSR_TBI_COPPER 0x000d
#define ESSR_TBI_FIBER 0x0005
