Module Name: src
Committed By: skrll
Date: Thu Jan 3 10:26:41 UTC 2019
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
src/sys/arch/arm/arm32: arm32_boot.c arm32_machdep.c cpu.c
src/sys/arch/arm/broadcom: bcm2835_intr.c
src/sys/arch/arm/fdt: cpu_fdt.c
src/sys/arch/arm/include: cpu.h
src/sys/arch/arm/include/arm32: machdep.h
Log Message:
Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.
Towards big.LITTLE support.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/arm32/arm32_boot.c
cvs rdiff -u -r1.124 -r1.125 src/sys/arch/arm/arm32/arm32_machdep.c \
src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/broadcom/bcm2835_intr.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/fdt/cpu_fdt.c
cvs rdiff -u -r1.99 -r1.100 src/sys/arch/arm/include/cpu.h
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/include/arm32/machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.4 src/sys/arch/arm/arm/armv6_start.S:1.5
--- src/sys/arch/arm/arm/armv6_start.S:1.4 Wed Jan 2 16:27:04 2019
+++ src/sys/arch/arm/arm/armv6_start.S Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.4 2019/01/02 16:27:04 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.5 2019/01/03 10:26:41 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -160,6 +160,12 @@ ENTRY_NP(generic_start)
#endif
#ifdef VERBOSE_INIT_ARM
+ VPRINTF("\n\rmidr :")
+ mrc p15, 0, r0, c0, c0, 0 // MIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rmpidr:")
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR
+ VPRINTX(r0)
VPRINTF("\n\rttb0 :")
mrc p15, 0, r0, c2, c0, 0 // TTBR0 read
VPRINTX(r0)
@@ -516,8 +522,14 @@ generic_startv6:
0)
-//
-// Perform the initialization of the an ARMv7 core required by NetBSD.
+/*
+ * Perform the initialization of the an ARMv7 core required by NetBSD.
+ *
+ * Uses the following callee saved registers:
+ *
+ * Callee saved:
+ * r4, r5, r6, r7
+ */
armv7_init:
.arch armv7a
@@ -618,6 +630,14 @@ armv7_init:
.ltorg
+/*
+ * Transititions the CPU to using the TTB passed in r0.
+ *
+ * Uses the following callee saved registers:
+ *
+ * Callee saved:
+ * r4, r5
+ */
armv7_mmuinit:
// Because the MMU may already be on do a typical sequence to set
@@ -740,22 +760,45 @@ ENTRY_NP(cpu_mpstart)
ldr R_TMP2, =start_stacks_top
sub sp, R_TMP2, R_VTOPDIFF
+#ifdef VERBOSE_INIT_ARM
+ VPRINTF("\n\rmidr :")
+ mrc p15, 0, r0, c0, c0, 0 // MIDR
+ VPRINTX(r0)
+ VPRINTF("\n\rmpidr:")
+ mrc p15, 0, r0, c0, c0, 5 // MPIDR
+ VPRINTX(r0)
+#endif
+
mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
+ and r4, #(MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
- mov r5, r4
- lsl r5, #INIT_ARM_STACK_SHIFT
- sub sp, sp, r5
+ mov r0, #0
+ ldr r1, =cpu_mpidr
+ sub r1, R_VTOPDIFF
+1:
+ ldr r2, [r1, r0, lsl #2] // r2 = cpu_mpidr[r0]
+ cmp r2, r4
+ beq 2f // found our mpidr
- XPUTC('c')
- mov r0, r4
- add r0, #'0'
- bl uartputc
- XPUTC(':')
+ add r0, #1
+ cmp r0, #MAXCPUS
+ bne 1b
+
+ // Not found our mpidr in the list - use Aff0 for cpuindex
+ and r0, r4, #7
+2:
+ mov R_TMP2, r0 // save cpu_index for later
- mov r0, sp
- bl generic_printx
+ VPRINTF("index: ")
+ VPRINTX(R_TMP2)
+ XPUTC('\n')
+ XPUTC('\r')
+
+ mov r5, R_TMP2
+ lsl r5, #INIT_ARM_STACK_SHIFT
+ sub sp, sp, r5
+ VPRINTX(sp)
XPUTC('\n')
XPUTC('\r')
@@ -776,21 +819,12 @@ ASEND(cpu_mpstart)
* Now running with real kernel VA via bootstrap tables
*/
armv7_mpcontinuation:
- ldr R_TMP2, =start_stacks_top
-
- mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
-
- mov r5, r4
- lsl r5, #INIT_ARM_STACK_SHIFT
- sub sp, R_TMP2, r5
+ // Adjust stack back to KVA address
+ add sp, sp, R_VTOPDIFF
VPRINTF("go\n\r")
- mrc p15, 0, r4, c0, c0, 5 // MPIDR get
- and r4, r4, #7 // get our cpu numder
-
- mov r0, r4
+ mov r0, R_TMP2 // index into cpu_mpidr[] or cpu_number if not found
bl cpu_init_secondary_processor
/* Wait for cpu_boot_secondary_processors the when cpu_info is allocated, etc */
@@ -799,7 +833,7 @@ armv7_mpcontinuation:
movt r6, #:upper16:arm_cpu_mbox
mov r5, #1 // bitmask...
- lsl r5, r4 // ... for our cpu
+ lsl r5, R_TMP2 // ... for our cpu
1: dmb // data memory barrier
ldr r2, [r6] // load mbox
@@ -809,7 +843,7 @@ armv7_mpcontinuation:
movw r0, #:lower16:cpu_info
movt r0, #:upper16:cpu_info // get pointer to cpu_infos
- ldr r5, [r0, r4, lsl #2] // load our cpu_info
+ ldr r5, [r0, R_TMP2, lsl #2] // load our cpu_info
ldr r6, [r5, #CI_IDLELWP] // get the idlelwp
ldr r7, [r6, #L_PCB] // now get its pcb
ldr sp, [r7, #PCB_KSP] // finally, we can load our SP
@@ -823,7 +857,7 @@ armv7_mpcontinuation:
str r6, [r5, #CI_CURLWP] // and note we are running on it
mov r0, r5 // pass cpu_info
- mov r1, r4 // pass cpu_id
+ mov r1, R_TMP2 // pass cpu_index
movw r2, #:lower16:MD_CPU_HATCH // pass md_cpu_hatch
movt r2, #:upper16:MD_CPU_HATCH // pass md_cpu_hatch
bl _C_LABEL(cpu_hatch)
Index: src/sys/arch/arm/arm32/arm32_boot.c
diff -u src/sys/arch/arm/arm32/arm32_boot.c:1.27 src/sys/arch/arm/arm32/arm32_boot.c:1.28
--- src/sys/arch/arm/arm32/arm32_boot.c:1.27 Wed Oct 31 09:31:01 2018
+++ src/sys/arch/arm/arm32/arm32_boot.c Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.27 2018/10/31 09:31:01 skrll Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -122,7 +122,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.27 2018/10/31 09:31:01 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
@@ -338,25 +338,25 @@ initarm_common(vaddr_t kvm_base, vsize_t
* of the idlelwp for this cpu.
*/
void
-cpu_hatch(struct cpu_info *ci, cpuid_t cpuid, void (*md_cpu_init)(struct cpu_info *))
+cpu_hatch(struct cpu_info *ci, u_int cpuindex, void (*md_cpu_init)(struct cpu_info *))
{
- KASSERT(cpu_index(ci) == cpuid);
+ KASSERT(cpu_index(ci) == cpuindex);
/*
* Raise our IPL to the max
*/
splhigh();
- VPRINTF("%s(%s): ", __func__, ci->ci_data.cpu_name);
+ VPRINTF("%s(%s): ", __func__, cpu_name(ci));
ci->ci_ctrl = armreg_sctlr_read();
uint32_t mpidr = armreg_mpidr_read();
if (mpidr & MPIDR_MT) {
- ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2;
+ ci->ci_smt_id = mpidr & MPIDR_AFF0;
+ ci->ci_core_id = mpidr & MPIDR_AFF1;
+ ci->ci_package_id = mpidr & MPIDR_AFF2;
} else {
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1;
+ ci->ci_core_id = mpidr & MPIDR_AFF0;
+ ci->ci_package_id = mpidr & MPIDR_AFF1;
}
/*
@@ -423,7 +423,7 @@ cpu_hatch(struct cpu_info *ci, cpuid_t c
VPRINTF(" done!\n");
/* Notify cpu_boot_secondary_processors that we're done */
- atomic_and_32(&arm_cpu_mbox, ~__BIT(cpuid));
+ atomic_and_32(&arm_cpu_mbox, ~__BIT(cpuindex));
membar_producer();
__asm __volatile("sev; sev; sev");
}
Index: src/sys/arch/arm/arm32/arm32_machdep.c
diff -u src/sys/arch/arm/arm32/arm32_machdep.c:1.124 src/sys/arch/arm/arm32/arm32_machdep.c:1.125
--- src/sys/arch/arm/arm32/arm32_machdep.c:1.124 Fri Oct 19 08:30:57 2018
+++ src/sys/arch/arm/arm32/arm32_machdep.c Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.124 2018/10/19 08:30:57 skrll Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.125 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.124 2018/10/19 08:30:57 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.125 2019/01/03 10:26:41 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_arm_start.h"
@@ -704,7 +704,7 @@ mm_md_physacc(paddr_t pa, vm_prot_t prot
vaddr_t
cpu_uarea_alloc_idlelwp(struct cpu_info *ci)
{
- const vaddr_t va = idlestack.pv_va + ci->ci_cpuid * USPACE;
+ const vaddr_t va = idlestack.pv_va + cpu_index(ci) * USPACE;
// printf("%s: %s: va=%lx\n", __func__, ci->ci_data.cpu_name, va);
return va;
}
@@ -723,13 +723,15 @@ cpu_uarea_alloc_idlelwp(struct cpu_info
*
*/
void
-cpu_init_secondary_processor(int cpuno)
+cpu_init_secondary_processor(int cpuindex)
{
// pmap_kernel has been sucessfully built and we can switch to it
cpu_domains(DOMAIN_DEFAULT);
cpu_idcache_wbinv_all();
+ VPRINTS("index: ");
+ VPRINTX(cpuindex);
VPRINTS(" ttb");
cpu_setup(boot_args);
@@ -763,9 +765,14 @@ cpu_init_secondary_processor(int cpuno)
VPRINTS(")");
VPRINTS(" (TTBCR=");
VPRINTX(armreg_ttbcr_read());
+ VPRINTS(")");
#endif
- atomic_or_uint(&arm_cpu_hatched, __BIT(cpuno));
+ atomic_or_uint(&arm_cpu_hatched, __BIT(cpuindex));
+
+ VPRINTS(" hatched=");
+ VPRINTX(arm_cpu_hatched);
+ VPRINTS("\n\r");
/* return to assembly to Wait for cpu_boot_secondary_processors */
}
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.124 src/sys/arch/arm/arm32/cpu.c:1.125
--- src/sys/arch/arm/arm32/cpu.c:1.124 Wed Jan 2 09:04:09 2019
+++ src/sys/arch/arm/arm32/cpu.c Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.124 2019/01/02 09:04:09 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.124 2019/01/02 09:04:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $");
#include <sys/param.h>
#include <sys/conf.h>
@@ -64,7 +64,9 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.12
extern const char *cpu_arch;
#ifdef MULTIPROCESSOR
-uint64_t cpu_mpidr[MAXCPUS];
+uint32_t cpu_mpidr[MAXCPUS] = {
+ [0 ... MAXCPUS - 1] = ~0,
+};
volatile u_int arm_cpu_hatched __cacheline_aligned = 0;
volatile uint32_t arm_cpu_mbox __cacheline_aligned = 0;
@@ -85,9 +87,10 @@ void
cpu_attach(device_t dv, cpuid_t id)
{
const char * const xname = device_xname(dv);
+ const int unit = device_unit(dv);
struct cpu_info *ci;
- if (id == 0) {
+ if (unit == 0) {
ci = curcpu();
/* Read SCTLR from cpu */
@@ -95,31 +98,38 @@ cpu_attach(device_t dv, cpuid_t id)
/* Get the CPU ID from coprocessor 15 */
+ ci->ci_cpuid = id;
ci->ci_arm_cpuid = cpu_idnum();
ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
+#ifdef MULTIPROCESSOR
+ ci->ci_mpidr = armreg_mpidr_read();
+#endif
} else {
#ifdef MULTIPROCESSOR
- KASSERT(cpu_info[id] == NULL);
+ KASSERT(cpu_info[unit] == NULL);
ci = kmem_zalloc(sizeof(*ci), KM_SLEEP);
ci->ci_cpl = IPL_HIGH;
ci->ci_cpuid = id;
- uint32_t mpidr = armreg_mpidr_read();
- if (mpidr & MPIDR_MT) {
- ci->ci_data.cpu_smt_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF1;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF2;
+ ci->ci_mpidr = armreg_mpidr_read();
+ if (ci->ci_mpidr & MPIDR_MT) {
+ ci->ci_smt_id = ci->ci_mpidr & MPIDR_AFF0;
+ ci->ci_core_id = ci->ci_mpidr & MPIDR_AFF1;
+ ci->ci_package_id = ci->ci_mpidr & MPIDR_AFF2;
} else {
- ci->ci_data.cpu_core_id = mpidr & MPIDR_AFF0;
- ci->ci_data.cpu_package_id = mpidr & MPIDR_AFF1;
+ ci->ci_core_id = ci->ci_mpidr & MPIDR_AFF0;
+ ci->ci_package_id = ci->ci_mpidr & MPIDR_AFF1;
}
ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq;
- ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid;
- ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype;
- ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev;
+
+ ci->ci_arm_cpuid = cpu_idnum();
+ ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
+ ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
+
ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2];
- cpu_info[ci->ci_cpuid] = ci;
- if ((arm_cpu_hatched & __BIT(id)) == 0) {
+
+ cpu_info[unit] = ci;
+ if ((arm_cpu_hatched & __BIT(unit)) == 0) {
ci->ci_dev = dv;
dv->dv_private = ci;
aprint_naive(": disabled\n");
@@ -180,7 +190,7 @@ cpu_attach(device_t dv, cpuid_t id)
/*
* and we are done if this is a secondary processor.
*/
- if (id != 0) {
+ if (unit != 0) {
#if 1
aprint_naive("\n");
aprint_normal("\n");
Index: src/sys/arch/arm/broadcom/bcm2835_intr.c
diff -u src/sys/arch/arm/broadcom/bcm2835_intr.c:1.15 src/sys/arch/arm/broadcom/bcm2835_intr.c:1.16
--- src/sys/arch/arm/broadcom/bcm2835_intr.c:1.15 Sun Dec 10 21:38:26 2017
+++ src/sys/arch/arm/broadcom/bcm2835_intr.c Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm2835_intr.c,v 1.15 2017/12/10 21:38:26 skrll Exp $ */
+/* $NetBSD: bcm2835_intr.c,v 1.16 2019/01/03 10:26:41 skrll Exp $ */
/*-
* Copyright (c) 2012, 2015 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.15 2017/12/10 21:38:26 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.16 2019/01/03 10:26:41 skrll Exp $");
#define _INTR_PRIVATE
@@ -288,7 +288,7 @@ bcm2835_irq_handler(void *frame)
{
struct cpu_info * const ci = curcpu();
const int oldipl = ci->ci_cpl;
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
const uint32_t oldipl_mask = __BIT(oldipl);
int ipl_mask = 0;
@@ -458,7 +458,7 @@ bcm2836mp_pic_unblock_irqs(struct pic_so
uint32_t irq_mask)
{
struct cpu_info * const ci = curcpu();
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
const bus_space_tag_t iot = bcml1icu_sc->sc_iot;
const bus_space_handle_t ioh = bcml1icu_sc->sc_ioh;
@@ -500,7 +500,7 @@ bcm2836mp_pic_block_irqs(struct pic_soft
uint32_t irq_mask)
{
struct cpu_info * const ci = curcpu();
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
const bus_space_tag_t iot = bcml1icu_sc->sc_iot;
const bus_space_handle_t ioh = bcml1icu_sc->sc_ioh;
@@ -534,7 +534,7 @@ static int
bcm2836mp_pic_find_pending_irqs(struct pic_softc *pic)
{
struct cpu_info * const ci = curcpu();
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
uint32_t lpending;
int ipl = 0;
@@ -577,7 +577,7 @@ static void bcm2836mp_cpu_init(struct pi
/* Enable IRQ and not FIQ */
bus_space_write_4(bcml1icu_sc->sc_iot, bcml1icu_sc->sc_ioh,
- BCM2836_LOCAL_MAILBOX_IRQ_CONTROLN(ci->ci_cpuid), 1);
+ BCM2836_LOCAL_MAILBOX_IRQ_CONTROLN(ci->ci_core_id), 1);
}
static void
@@ -597,7 +597,7 @@ int
bcm2836mp_ipi_handler(void *priv)
{
const struct cpu_info *ci = curcpu();
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
uint32_t ipimask, bit;
ipimask = bus_space_read_4(bcml1icu_sc->sc_iot, bcml1icu_sc->sc_ioh,
@@ -644,7 +644,7 @@ bcm2836mp_ipi_handler(void *priv)
static void
bcm2836mp_intr_init(void *priv, struct cpu_info *ci)
{
- const cpuid_t cpuid = ci->ci_cpuid;
+ const cpuid_t cpuid = ci->ci_core_id;
struct pic_softc * const pic = &bcm2836mp_pic[cpuid];
#if defined(MULTIPROCESSOR)
Index: src/sys/arch/arm/fdt/cpu_fdt.c
diff -u src/sys/arch/arm/fdt/cpu_fdt.c:1.17 src/sys/arch/arm/fdt/cpu_fdt.c:1.18
--- src/sys/arch/arm/fdt/cpu_fdt.c:1.17 Wed Jan 2 16:13:49 2019
+++ src/sys/arch/arm/fdt/cpu_fdt.c Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_fdt.c,v 1.17 2019/01/02 16:13:49 skrll Exp $ */
+/* $NetBSD: cpu_fdt.c,v 1.18 2019/01/03 10:26:41 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -30,7 +30,7 @@
#include "psci_fdt.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.17 2019/01/02 16:13:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.18 2019/01/03 10:26:41 skrll Exp $");
#include <sys/param.h>
#include <sys/atomic.h>
@@ -110,16 +110,6 @@ cpu_fdt_match(device_t parent, cfdata_t
case ARM_CPU_ARMV8:
if (fdtbus_get_reg(phandle, 0, &mpidr, NULL) != 0)
return 0;
-
-#ifndef __aarch64__
- /* XXX NetBSD/arm requires all CPUs to be in the same cluster */
- const u_int bp_clid = cpu_clusterid();
- const u_int clid = __SHIFTOUT(mpidr, MPIDR_AFF1);
-
- if (bp_clid != clid)
- return 0;
-#endif
- break;
default:
break;
}
@@ -149,9 +139,6 @@ cpu_fdt_attach(device_t parent, device_t
aprint_error(": missing 'reg' property\n");
return;
}
-#ifndef __aarch64__
- mpidr = __SHIFTOUT(mpidr, MPIDR_AFF0);
-#endif
cpuid = mpidr;
break;
default:
@@ -261,12 +248,6 @@ arm_fdt_cpu_bootstrap(void)
if (mpidr == bp_mpidr)
continue; /* BP already started */
-#ifdef __arm__
- /* XXX NetBSD/arm requires all CPUs to be in the same cluster */
- if ((mpidr & ~MPIDR_AFF0) != (bp_mpidr & ~MPIDR_AFF0))
- continue;
-#endif
-
KASSERT(cpuindex < MAXCPUS);
cpu_mpidr[cpuindex] = mpidr;
cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
@@ -313,15 +294,10 @@ arm_fdt_cpu_mpstart(void)
if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
continue;
+
if (mpidr == bp_mpidr)
continue; /* BP already started */
-#ifdef __arm__
- /* XXX NetBSD/arm requires all CPUs to be in the same cluster */
- if ((mpidr & ~MPIDR_AFF0) != (bp_mpidr & ~MPIDR_AFF0))
- continue;
-#endif
-
method = fdtbus_get_string(child, "enable-method");
if (method == NULL)
continue;
Index: src/sys/arch/arm/include/cpu.h
diff -u src/sys/arch/arm/include/cpu.h:1.99 src/sys/arch/arm/include/cpu.h:1.100
--- src/sys/arch/arm/include/cpu.h:1.99 Thu Oct 25 07:13:55 2018
+++ src/sys/arch/arm/include/cpu.h Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.99 2018/10/25 07:13:55 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.100 2019/01/03 10:26:41 skrll Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -175,6 +175,12 @@ struct cpu_info {
struct evcnt ci_und_cp15_ev;
struct evcnt ci_vfp_evs[3];
+ uint32_t ci_midr;
+ uint32_t ci_mpidr;
+
+ struct arm_cache_info *
+ ci_cacheinfo;
+
#if defined(MP_CPU_INFO_MEMBERS)
MP_CPU_INFO_MEMBERS
#endif
@@ -248,7 +254,7 @@ extern struct cpu_info *cpu_info[];
#if defined(MULTIPROCESSOR)
extern volatile u_int arm_cpu_hatched;
-extern uint64_t cpu_mpidr[];
+extern uint32_t cpu_mpidr[];
void cpu_mpstart(void);
void cpu_init_secondary_processor(int);
Index: src/sys/arch/arm/include/arm32/machdep.h
diff -u src/sys/arch/arm/include/arm32/machdep.h:1.27 src/sys/arch/arm/include/arm32/machdep.h:1.28
--- src/sys/arch/arm/include/arm32/machdep.h:1.27 Thu Oct 18 09:01:52 2018
+++ src/sys/arch/arm/include/arm32/machdep.h Thu Jan 3 10:26:41 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.h,v 1.27 2018/10/18 09:01:52 skrll Exp $ */
+/* $NetBSD: machdep.h,v 1.28 2019/01/03 10:26:41 skrll Exp $ */
#ifndef _ARM32_MACHDEP_H_
#define _ARM32_MACHDEP_H_
@@ -57,7 +57,7 @@ extern u_long kern_vtopdiff;
/* misc prototypes used by the many arm machdeps */
void cortex_pmc_ccnt_init(void);
-void cpu_hatch(struct cpu_info *, cpuid_t, void (*)(struct cpu_info *));
+void cpu_hatch(struct cpu_info *, u_int, void (*)(struct cpu_info *));
void halt(void);
void parse_mi_bootargs(char *);
void data_abort_handler(trapframe_t *);
