Module Name: src
Committed By: jmcneill
Date: Sun Jan 20 17:29:04 UTC 2019
Modified Files:
src/sys/arch/arm/dts: meson8b.dtsi
Log Message:
Add operating points and clocks for CPUs
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/dts/meson8b.dtsi
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/dts/meson8b.dtsi
diff -u src/sys/arch/arm/dts/meson8b.dtsi:1.3 src/sys/arch/arm/dts/meson8b.dtsi:1.4
--- src/sys/arch/arm/dts/meson8b.dtsi:1.3 Sun Jan 20 00:44:01 2019
+++ src/sys/arch/arm/dts/meson8b.dtsi Sun Jan 20 17:29:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: meson8b.dtsi,v 1.3 2019/01/20 00:44:01 jmcneill Exp $ */
+/* $NetBSD: meson8b.dtsi,v 1.4 2019/01/20 17:29:04 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <jmcne...@invisible.ca>
@@ -43,6 +43,84 @@
<0xd0100000 0x100000>; /* VPU */
status = "disabled";
};
+
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-96000000 {
+ opp-hz = /bits/ 64 <96000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-504000000 {
+ opp-hz = /bits/ 64 <504000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <860000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1140000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1140000>;
+ };
+ opp-1320000000 {
+ opp-hz = /bits/ 64 <1320000000>;
+ opp-microvolt = <1140000>;
+ };
+ opp-1488000000 {
+ opp-hz = /bits/ 64 <1488000000>;
+ opp-microvolt = <1140000>;
+ };
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-microvolt = <1140000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPUCLK>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPUCLK>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPUCLK>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPUCLK>;
};
&pinctrl_cbus {
