Module Name: src
Committed By: alnsn
Date: Tue Jan 22 01:25:53 UTC 2019
Modified Files:
src/sys/rump/kern/lib/libsljit/arch/mips: cache.c
Log Message:
Cast register_t to uintptr_t before casting to void *.
Not sure what's going on here but evbmips64-el build fails
without this cast.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/rump/kern/lib/libsljit/arch/mips/cache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/rump/kern/lib/libsljit/arch/mips/cache.c
diff -u src/sys/rump/kern/lib/libsljit/arch/mips/cache.c:1.2 src/sys/rump/kern/lib/libsljit/arch/mips/cache.c:1.3
--- src/sys/rump/kern/lib/libsljit/arch/mips/cache.c:1.2 Tue Jan 22 00:36:02 2019
+++ src/sys/rump/kern/lib/libsljit/arch/mips/cache.c Tue Jan 22 01:25:53 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.2 2019/01/22 00:36:02 alnsn Exp $ */
+/* $NetBSD: cache.c,v 1.3 2019/01/22 01:25:53 alnsn Exp $ */
/*-
* Copyright (c) 2014 Alexander Nasonov.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.2 2019/01/22 00:36:02 alnsn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.3 2019/01/22 01:25:53 alnsn Exp $");
/*
* Barebone implementation of mips cache routines for rump.
@@ -48,5 +48,5 @@ static void
icache_sync_range(register_t va, vsize_t sz)
{
- (void)rumpcomp_sync_icache((void *)va, (uint64_t)sz);
+ (void)rumpcomp_sync_icache((void *)(uintptr_t)va, (uint64_t)sz);
}
