Module Name: src
Committed By: jmcneill
Date: Sun Apr 21 13:08:48 UTC 2019
Modified Files:
src/sys/arch/arm/amlogic: mesongx_mmc.c
Log Message:
Fix module clock rate in DDR52 mode and support mmc-ddr-3_3v DT property
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/amlogic/mesongx_mmc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/mesongx_mmc.c
diff -u src/sys/arch/arm/amlogic/mesongx_mmc.c:1.4 src/sys/arch/arm/amlogic/mesongx_mmc.c:1.5
--- src/sys/arch/arm/amlogic/mesongx_mmc.c:1.4 Sat Mar 16 12:52:47 2019
+++ src/sys/arch/arm/amlogic/mesongx_mmc.c Sun Apr 21 13:08:48 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongx_mmc.c,v 1.4 2019/03/16 12:52:47 jmcneill Exp $ */
+/* $NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.4 2019/03/16 12:52:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -463,7 +463,7 @@ mesongx_mmc_set_clock(struct mesongx_mmc
best_sel = 0;
best_div = 0;
- const u_int target_rate = (freq * 1000) >> ddr;
+ const u_int target_rate = (freq * 1000) << ddr;
for (sel = 0; sel <= 1; sel++) {
const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]);
for (div = 1; div <= 63; div++) {
@@ -541,6 +541,10 @@ mesongx_mmc_attach_i(device_t self)
if (of_getprop_bool(sc->sc_phandle, "cap-mmc-highspeed"))
saa.saa_caps |= SMC_CAPS_MMC_HIGHSPEED;
+ if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-3_3v")) {
+ saa.saa_caps |= SMC_CAPS_MMC_DDR52;
+ }
+
if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-1_8v")) {
saa.saa_caps |= SMC_CAPS_MMC_DDR52;
sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V;
