Module Name: src
Committed By: skrll
Date: Thu May 2 11:49:04 UTC 2019
Modified Files:
src/sys/arch/arm/include: armreg.h
Log Message:
Fix Normal Region Remap Register bitmask names
To generate a diff of this commit:
cvs rdiff -u -r1.125 -r1.126 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.125 src/sys/arch/arm/include/armreg.h:1.126
--- src/sys/arch/arm/include/armreg.h:1.125 Wed Jan 30 02:02:23 2019
+++ src/sys/arch/arm/include/armreg.h Thu May 2 11:49:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.125 2019/01/30 02:02:23 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.126 2019/05/02 11:49:04 skrll Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -523,12 +523,12 @@
#define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
#define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset
-#define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
-#define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
-#define NRRR_NC 0 // non-cacheable
-#define NRRR_WB_WA 1 // write-back write-allocate
-#define NRRR_WT 2 // write-through
-#define NRRR_WB 3 // write-back
+#define NMRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings
+#define NMRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings
+#define NMRR_NC 0 // non-cacheable
+#define NMRR_WBWA 1 // write-back write-allocate
+#define NMRR_WT 2 // write-through
+#define NMRR_WB 3 // write-back
#define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable
#define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
#define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
@@ -870,8 +870,8 @@ ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,
/* cp10 c10 registers */
ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */
-ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
-ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
+ARMREG_READ_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
+ARMREG_WRITE_INLINE(nmrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */
/* cp15 c13 registers */
ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */
