Module Name: src
Committed By: tsutsui
Date: Wed Dec 11 16:16:13 UTC 2019
Modified Files:
src/sys/arch/emips/emips: interrupt.c
Log Message:
Fix a longstanding "freeze right after enabling interrupt" problem.
With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.
Should be pulled up to netbsd-9.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/emips/emips/interrupt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/emips/emips/interrupt.c
diff -u src/sys/arch/emips/emips/interrupt.c:1.7 src/sys/arch/emips/emips/interrupt.c:1.8
--- src/sys/arch/emips/emips/interrupt.c:1.7 Mon Dec 9 16:19:11 2019
+++ src/sys/arch/emips/emips/interrupt.c Wed Dec 11 16:16:13 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $ */
+/* $NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -102,6 +102,19 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
curcpu()->ci_data.cpu_nintr++;
+#if 0
+ /*
+ * According to Giano simulator sources (Cpus/mips_cpu.cpp),
+ * interrupt register bits in CAUSE register are updated
+ * only when the exception is triggered. This means checking
+ * CAUSE register via splintr() in a while loop in this
+ * interrupt handler doesn't work as expected on Giano.
+ *
+ * I don't know whether the real FPGA eMIPS has the same
+ * design as the Giano simulator, but for now I'd like to
+ * choose 'call only one handler per each interrupt' strategy,
+ * as the original NetBSD/emips implementation.
+ */
while (ppl < (ipl = splintr(&ipending))) {
splx(ipl);
/* device interrupts */
@@ -110,6 +123,14 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
}
(void)splhigh();
}
+#else
+ ipl = splintr(&ipending);
+ __USE(ipl);
+ /* device interrupts */
+ if (ipending & MIPS_INT_MASK_5) {
+ (*platform.iointr)(status, pc, ipending);
+ }
+#endif
}
/*
