Module Name: src
Committed By: maxv
Date: Tue Jan 28 17:23:30 UTC 2020
Modified Files:
src/sys/arch/aarch64/include: armreg.h
Log Message:
More definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.30 src/sys/arch/aarch64/include/armreg.h:1.31
--- src/sys/arch/aarch64/include/armreg.h:1.30 Sat Dec 28 00:22:08 2019
+++ src/sys/arch/aarch64/include/armreg.h Tue Jan 28 17:23:30 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.30 2019/12/28 00:22:08 rjs Exp $ */
+/* $NetBSD: armreg.h,v 1.31 2020/01/28 17:23:30 maxv Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -229,6 +229,45 @@ AARCH64REG_READ_INLINE(id_aa64isar0_el1)
#define ID_AA64ISAR0_EL1_AES_PMUL 2
AARCH64REG_READ_INLINE(id_aa64isar1_el1)
+
+#define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
+#define ID_AA64ISAR1_EL1_SPECRES_NONE 0
+#define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_SB __BITS(39,36)
+#define ID_AA64ISAR1_EL1_SB_NONE 0
+#define ID_AA64ISAR1_EL1_SB_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)
+#define ID_AA64ISAR1_EL1_FRINTTS_NONE 0
+#define ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_GPI __BITS(31,28)
+#define ID_AA64ISAR1_EL1_GPI_NONE 0
+#define ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_GPA __BITS(27,24)
+#define ID_AA64ISAR1_EL1_GPA_NONE 0
+#define ID_AA64ISAR1_EL1_GPA_QARMA 1
+#define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)
+#define ID_AA64ISAR1_EL1_LRCPC_NONE 0
+#define ID_AA64ISAR1_EL1_LRCPC_PR 1
+#define ID_AA64ISAR1_EL1_LRCPC_PR_UR 2
+#define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)
+#define ID_AA64ISAR1_EL1_FCMA_NONE 0
+#define ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)
+#define ID_AA64ISAR1_EL1_JSCVT_NONE 0
+#define ID_AA64ISAR1_EL1_JSCVT_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_API __BITS(11,8)
+#define ID_AA64ISAR1_EL1_API_NONE 0
+#define ID_AA64ISAR1_EL1_API_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_API_ENHANCED 2
+#define ID_AA64ISAR1_EL1_APA __BITS(7,4)
+#define ID_AA64ISAR1_EL1_APA_NONE 0
+#define ID_AA64ISAR1_EL1_APA_QARMA 1
+#define ID_AA64ISAR1_EL1_APA_QARMA_ENH 2
+#define ID_AA64ISAR1_EL1_DPB __BITS(3,0)
+#define ID_AA64ISAR1_EL1_DPB_NONE 0
+#define ID_AA64ISAR1_EL1_DPB_CVAP 1
+#define ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
+
AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
#define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)
@@ -260,11 +299,106 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
#define ID_AA64MMFR0_EL1_PARANGE_16T 4
#define ID_AA64MMFR0_EL1_PARANGE_256T 5
-AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
+
+#define ID_AA64MMFR1_EL1_XNX __BITS(31,28)
+#define ID_AA64MMFR1_EL1_XNX_NONE 0
+#define ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
+#define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)
+#define ID_AA64MMFR1_EL1_SPECSEI_NONE 0
+#define ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
+#define ID_AA64MMFR1_EL1_PAN __BITS(23,20)
+#define ID_AA64MMFR1_EL1_PAN_NONE 0
+#define ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
+#define ID_AA64MMFR1_EL1_PAN_S1E1 2
+#define ID_AA64MMFR1_EL1_LO __BITS(19,16)
+#define ID_AA64MMFR1_EL1_LO_NONE 0
+#define ID_AA64MMFR1_EL1_LO_SUPPORTED 1
+#define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)
+#define ID_AA64MMFR1_EL1_HPDS_NONE 0
+#define ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
+#define ID_AA64MMFR1_EL1_HPDS_EXTRA_PTD 2
+#define ID_AA64MMFR1_EL1_VH __BITS(11,8)
+#define ID_AA64MMFR1_EL1_VH_NONE 0
+#define ID_AA64MMFR1_EL1_VH_SUPPORTED 1
+#define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)
+#define ID_AA64MMFR1_EL1_VMIDBITS_8BIT 0
+#define ID_AA64MMFR1_EL1_VMIDBITS_16BIT 2
+#define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)
+#define ID_AA64MMFR1_EL1_HAFDBS_NONE 0
+#define ID_AA64MMFR1_EL1_HAFDBS_A 1
+#define ID_AA64MMFR1_EL1_HAFDBS_AD 2
+
AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
+
+#define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)
+#define ID_AA64MMFR2_EL1_E0PD_NONE 0
+#define ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_EVT __BITS(59,56)
+#define ID_AA64MMFR2_EL1_EVT_NONE 0
+#define ID_AA64MMFR2_EL1_EVT_TO_TI 1
+#define ID_AA64MMFR2_EL1_EVT_TO_TI_TTL 2
+#define ID_AA64MMFR2_EL1_BBM __BITS(55,52)
+#define ID_AA64MMFR2_EL1_BBM_L0 0
+#define ID_AA64MMFR2_EL1_BBM_L1 1
+#define ID_AA64MMFR2_EL1_BBM_L2 2
+#define ID_AA64MMFR2_EL1_TTL __BITS(51,48)
+#define ID_AA64MMFR2_EL1_TTL_NONE 0
+#define ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_FWB __BITS(43,40)
+#define ID_AA64MMFR2_EL1_FWB_NONE 0
+#define ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_IDS __BITS(39,36)
+#define ID_AA64MMFR2_EL1_IDS_0X0 0
+#define ID_AA64MMFR2_EL1_IDS_0X18 1
+#define ID_AA64MMFR2_EL1_AT __BITS(35,32)
+#define ID_AA64MMFR2_EL1_AT_NONE 0
+#define ID_AA64MMFR2_EL1_AT_16BIT 1
+#define ID_AA64MMFR2_EL1_ST __BITS(31,28)
+#define ID_AA64MMFR2_EL1_ST_39 0
+#define ID_AA64MMFR2_EL1_ST_48 1
+#define ID_AA64MMFR2_EL1_NV __BITS(27,24)
+#define ID_AA64MMFR2_EL1_NV_NONE 0
+#define ID_AA64MMFR2_EL1_NV_HCR 1
+#define ID_AA64MMFR2_EL1_NV_HCR_VNCR 2
+#define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)
+#define ID_AA64MMFR2_EL1_CCIDX_32BIT 0
+#define ID_AA64MMFR2_EL1_CCIDX_64BIT 1
+#define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)
+#define ID_AA64MMFR2_EL1_VARANGE_48BIT 0
+#define ID_AA64MMFR2_EL1_VARANGE_52BIT 1
+#define ID_AA64MMFR2_EL1_IESB __BITS(15,12)
+#define ID_AA64MMFR2_EL1_IESB_NONE 0
+#define ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_LSM __BITS(11,8)
+#define ID_AA64MMFR2_EL1_LSM_NONE 0
+#define ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_UAO __BITS(7,4)
+#define ID_AA64MMFR2_EL1_UAO_NONE 0
+#define ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
+#define ID_AA64MMFR2_EL1_CNP __BITS(3,0)
+#define ID_AA64MMFR2_EL1_CNP_NONE 0
+#define ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
+
+AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
AARCH64REG_READ_INLINE(id_aa64pfr1_el1)
+
+#define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)
+#define ID_AA64PFR1_EL1_RASFRAC_NORMAL 0
+#define ID_AA64PFR1_EL1_RASFRAC_EXTRA 1
+#define ID_AA64PFR1_EL1_MTE __BITS(11,8)
+#define ID_AA64PFR1_EL1_MTE_NONE 0
+#define ID_AA64PFR1_EL1_MTE_PARTIAL 1
+#define ID_AA64PFR1_EL1_MTE_SUPPORTED 2
+#define ID_AA64PFR1_EL1_SSBS __BITS(7,4)
+#define ID_AA64PFR1_EL1_SSBS_NONE 0
+#define ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
+#define ID_AA64PFR1_EL1_SSBS_MSR_MRS 2
+#define ID_AA64PFR1_EL1_BT __BITS(3,0)
+#define ID_AA64PFR1_EL1_BT_NONE 0
+#define ID_AA64PFR1_EL1_BT_SUPPORTED 1
+
AARCH64REG_READ_INLINE(id_aa64zfr0_el1)
AARCH64REG_READ_INLINE(id_pfr1_el1)
AARCH64REG_READ_INLINE(isr_el1)
