Module Name: src
Committed By: martin
Date: Thu Mar 19 19:05:34 UTC 2020
Modified Files:
src/sys/dev/pci [netbsd-9]: pci_subr.c pcireg.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #782):
sys/dev/pci/pcireg.h: revision 1.150
sys/dev/pci/pcireg.h: revision 1.151
sys/dev/pci/pci_subr.c: revision 1.220
sys/dev/pci/pci_subr.c: revision 1.221
sys/dev/pci/pcireg.h: revision 1.149
- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.
Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
Remove unused shift and mask definitions.
Add comment.
To generate a diff of this commit:
cvs rdiff -u -r1.215.2.2 -r1.215.2.3 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.147.4.1 -r1.147.4.2 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.215.2.2 src/sys/dev/pci/pci_subr.c:1.215.2.3
--- src/sys/dev/pci/pci_subr.c:1.215.2.2 Tue Jan 21 15:15:23 2020
+++ src/sys/dev/pci/pci_subr.c Thu Mar 19 19:05:34 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.215.2.2 2020/01/21 15:15:23 martin Exp $ */
+/* $NetBSD: pci_subr.c,v 1.215.2.3 2020/03/19 19:05:34 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.2 2020/01/21 15:15:23 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.3 2020/03/19 19:05:34 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1869,6 +1869,9 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
printf(" Max Read Request Size: %d byte\n",
128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
+ if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI)
+ onoff("Bridge Config Retry Enable", reg,
+ PCIE_DCSR_BRDG_CFG_RETRY);
/* Device Status Register */
reg = regs[o2i(capoff + PCIE_DCSR)];
@@ -2162,6 +2165,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("Reserved\n");
break;
}
+ onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);
+ onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);
printf(" OBFF Supported: ");
switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
case 0x0:
@@ -2214,6 +2219,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
onoff("Emergency Power Reduction Request", reg,
PCIE_DCSR2_EMGPWRRED_REQ);
+ onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);
printf(" OBFF: ");
switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
case 0x0:
@@ -2254,6 +2260,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
pci_print_pcie_linkspeedvector(
__SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
printf("\n");
+ onoff("Retimer Presence Detect Supported", reg,
+ PCIE_LCAP2_RETIMERPD);
onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
}
@@ -2273,7 +2281,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
__SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));
printf("\n");
printf(" Transmit Margin: %u\n",
- (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
+ (unsigned int)__SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN));
onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
printf(" Compliance Present/De-emphasis: ");
@@ -4160,6 +4168,24 @@ pci_conf_print_ptm_cap(const pcireg_t *r
/* XXX pci_conf_print_rtr_cap */
/* XXX pci_conf_print_desigvndsp_cap */
/* XXX pci_conf_print_vf_resizbar_cap */
+
+static void
+pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff)
+{
+ pcireg_t reg;
+
+ printf("\n Data link Feature Register\n");
+ reg = regs[o2i(extcapoff + PCI_DLF_CAP)];
+ printf(" Capability register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG);
+
+ reg = regs[o2i(extcapoff + PCI_DLF_STAT)];
+ printf(" Status register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID);
+}
+
/* XXX pci_conf_print_hierarchyid_cap */
/* XXX pci_conf_print_npem_cap */
@@ -4246,8 +4272,8 @@ static struct {
NULL },
{ PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
NULL },
- { 0x25, "unknown", NULL },
- { 0x26, "unknown", NULL },
+ { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
+ { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL },
{ 0x27, "unknown", NULL },
{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
NULL },
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.147.4.1 src/sys/dev/pci/pcireg.h:1.147.4.2
--- src/sys/dev/pci/pcireg.h:1.147.4.1 Tue Jan 21 15:15:23 2020
+++ src/sys/dev/pci/pcireg.h Thu Mar 19 19:05:34 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.147.4.1 2020/01/21 15:15:23 martin Exp $ */
+/* $NetBSD: pcireg.h,v 1.147.4.2 2020/03/19 19:05:34 martin Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -603,7 +603,7 @@ typedef u_int8_t pci_revision_t;
#define PCI_PMCSR_PME_EN 0x00000100
#define PCI_PMCSR_DATASEL_MASK 0x00001e00
#define PCI_PMCSR_DATASCL_MASK 0x00006000
-#define PCI_PMCSR_PME_STS 0x00008000
+#define PCI_PMCSR_PME_STS 0x00008000 /* PME Status (R/W1C) */
#define PCI_PMCSR_B2B3_SUPPORT 0x00400000
#define PCI_PMCSR_BPCC_EN 0x00800000
#define PCI_PMCSR_DATA 0xff000000
@@ -1097,6 +1097,8 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */
+#define PCIE_DCAP2_TBT_COMP __BIT(16) /* 10-bit Tag Completer Supp. */
+#define PCIE_DCAP2_TBT_REQ __BIT(17) /* 10-bit Tag Requester Supp. */
#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
@@ -1114,6 +1116,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */
#define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */
#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */
+#define PCIE_DCSR2_TBT_REQ __BIT(12) /* 10-bit Tag Requester Ena. */
#define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */
#define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */
#define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */
@@ -1525,6 +1528,8 @@ struct pci_rom {
#define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */
#define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */
#define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */
+#define PCI_EXTCAP_DLF 0x0025 /* Data link Feature */
+#define PCI_EXTCAP_PYSLAY_16GT 0x0026 /* Physical Layer 16.0 GT/s */
#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
@@ -1568,8 +1573,6 @@ struct pci_rom {
/* Shares bits with COR_STATUS */
#define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */
#define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0)
-#define PCI_AER_FIRST_ERROR_PTR_S 0
-#define PCI_AER_FIRST_ERROR_PTR_M 0x1f
#define PCI_AER_ECRC_GEN_CAPABLE __BIT(5)
#define PCI_AER_ECRC_GEN_ENABLE __BIT(6)
#define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7)
@@ -1594,15 +1597,9 @@ struct pci_rom {
#define PCI_AER_ROOTERR_NF_ERR __BIT(5)
#define PCI_AER_ROOTERR_F_ERR __BIT(6)
#define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27)
-#define PCI_AER_ROOTERR_INT_MESSAGE_S 27
-#define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f
#define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */
#define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0)
-#define PCI_AER_ERRSRC_ID_ERR_COR_S 0
-#define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff
#define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16)
-#define PCI_AER_ERRSRC_ID_ERR_UC_S 16
-#define PCI_AER_ERRSRC_ID_ERR_UC_M 0xffff
/* Only for root complex ports */
#define PCI_AER_TLP_PREFIX_LOG 0x38 /*TLP Prefix Log Register */
/* Only for TLP prefix functions */
@@ -1613,31 +1610,19 @@ struct pci_rom {
*/
#define PCI_VC_CAP1 0x04 /* Port VC Capability Register 1 */
#define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0)
-#define PCI_VC_CAP1_EXT_COUNT_S 0
-#define PCI_VC_CAP1_EXT_COUNT_M 0x7
#define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4)
-#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_S 4
-#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_M 0x7
#define PCI_VC_CAP1_REFCLK __BITS(9, 8)
-#define PCI_VC_CAP1_REFCLK_S 8
-#define PCI_VC_CAP1_REFCLK_M 0x3
#define PCI_VC_CAP1_REFCLK_100NS 0x0
#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10)
-#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_S 10
-#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_M 0x3
#define PCI_VC_CAP2 0x08 /* Port VC Capability Register 2 */
#define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
#define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1)
#define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2)
#define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3)
#define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24)
-#define PCI_VC_CAP2_ARB_TABLE_OFFSET_S 24
-#define PCI_VC_CAP2_ARB_TABLE_OFFSET_M 0xff
#define PCI_VC_CONTROL 0x0c /* Port VC Control Register (16bit) */
#define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0)
#define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1)
-#define PCI_VC_CONTROL_VC_ARB_SELECT_S 1
-#define PCI_VC_CONTROL_VC_ARB_SELECT_M 0x7
#define PCI_VC_STATUS 0x0e /* Port VC Status Register (16bit) */
#define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0)
#define PCI_VC_RESOURCE_CAP(n) (0x10 + ((n) * 0x0c)) /* VC Resource Capability Register */
@@ -1650,22 +1635,12 @@ struct pci_rom {
#define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14)
#define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15)
#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16)
-#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_S 16
-#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_M 0x7f
#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24)
-#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S 24
-#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_M 0xff
#define PCI_VC_RESOURCE_CTL(n) (0x14 + ((n) * 0x0c)) /* VC Resource Control Register */
#define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0)
-#define PCI_VC_RESOURCE_CTL_TCVC_MAP_S 0
-#define PCI_VC_RESOURCE_CTL_TCVC_MAP_M 0xff
#define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16)
#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17)
-#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_S 17
-#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_M 0x7
#define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24)
-#define PCI_VC_RESOURCE_CTL_VC_ID_S 24
-#define PCI_VC_RESOURCE_CTL_VC_ID_M 0x7
#define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31)
#define PCI_VC_RESOURCE_STA(n) (0x18 + ((n) * 0x0c)) /* VC Resource Status Register */
#define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0)
@@ -1820,8 +1795,6 @@ struct pci_rom {
#define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0)
#define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1)
#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21)
-#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_S 21
-#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_M 0x7ff
#define PCI_SRIOV_CTL 0x08 /* SR-IOV Control (16bit) */
#define PCI_SRIOV_CTL_VF_ENABLE __BIT(0)
#define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1)
@@ -1844,11 +1817,7 @@ struct pci_rom {
#define PCI_SRIOV_BAR(x) (PCI_SRIOV_BARS + ((x) * 4))
#define PCI_SRIOV_VF_MIG_STA_AR 0x3c /* VF Migration State Array Offset */
#define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3)
-#define PCI_SRIOV_VF_MIG_STA_OFFSET_S 3
-#define PCI_SRIOV_VF_MIG_STA_OFFSET_M 0x1fffffff
#define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0)
-#define PCI_SRIOV_VF_MIG_STA_BIR_S 0
-#define PCI_SRIOV_VF_MIG_STA_BIR_M 0x7
/*
* Extended capability ID: 0x0011
@@ -2187,6 +2156,23 @@ struct pci_rom {
*/
/*
+ * Extended capability ID: 0x0025
+ * Data link Feature
+ */
+#define PCI_DLF_CAP 0x04 /* Capability register */
+#define PCI_DLF_LFEAT __BITS(22, 0) /* Local DLF supported */
+#define PCI_DLF_LFEAT_SCLFCTL __BIT(0) /* Scaled Flow Control */
+#define PCI_DLF_CAP_XCHG __BIT(31) /* DLF Exchange enable */
+#define PCI_DLF_STAT 0x08 /* Status register */
+ /* Bit 22:0 is the same as PCI_DLF_CAP_LINKFEAT */
+#define PCI_DLF_STAT_RMTVALID __BIT(31) /* Remote DLF supported Valid */
+
+/*
+ * Extended capability ID: 0x0026
+ * Physical Layer 16.0 GT/s
+ */
+
+/*
* Extended capability ID: 0x0028
* Hierarchy ID
*/
