Module Name: src
Committed By: msaitoh
Date: Tue Mar 24 03:45:26 UTC 2020
Modified Files:
src/sys/dev/ic: spdmem.c spdmemvar.h
Log Message:
- Define some new parameters of DDR3 SPD ROM.
- Use fine timebase parameters for time calculation on DDR3. This change
makes PC3-XXXX vaule more correctly on newer DDR3.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/dev/ic/spdmem.c
cvs rdiff -u -r1.14 -r1.15 src/sys/dev/ic/spdmemvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/spdmem.c
diff -u src/sys/dev/ic/spdmem.c:1.33 src/sys/dev/ic/spdmem.c:1.34
--- src/sys/dev/ic/spdmem.c:1.33 Tue Mar 24 03:35:25 2020
+++ src/sys/dev/ic/spdmem.c Tue Mar 24 03:45:25 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: spdmem.c,v 1.33 2020/03/24 03:35:25 msaitoh Exp $ */
+/* $NetBSD: spdmem.c,v 1.34 2020/03/24 03:45:25 msaitoh Exp $ */
/*
* Copyright (c) 2007 Nicolas Joly
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.33 2020/03/24 03:35:25 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.34 2020/03/24 03:45:25 msaitoh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -756,6 +756,30 @@ print_part(const char *part, size_t pnsi
aprint_normal(": %.*s\n", (int)(p - part), part);
}
+static u_int
+ddr3_value_pico(struct spdmem *s, uint8_t txx_mtb, uint8_t txx_ftb)
+{
+ u_int mtb, ftb; /* in picoseconds */
+ intmax_t signed_txx_ftb;
+ u_int val;
+
+ mtb = (u_int)s->sm_ddr3.ddr3_mtb_dividend * 1000 /
+ s->sm_ddr3.ddr3_mtb_divisor;
+ ftb = (u_int)s->sm_ddr3.ddr3_ftb_dividend * 1000 /
+ s->sm_ddr3.ddr3_ftb_divisor;
+
+ /* tXX_ftb is signed value */
+ signed_txx_ftb = (int8_t)txx_ftb;
+ val = txx_mtb * mtb +
+ ((txx_ftb > 127) ? signed_txx_ftb : txx_ftb) * ftb / 1000;
+
+ return val;
+}
+
+#define __DDR3_VALUE_PICO(s, field) \
+ ddr3_value_pico(s, s->sm_ddr3.ddr3_##field##_mtb, \
+ s->sm_ddr3.ddr3_##field##_ftb)
+
static void
decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s)
{
@@ -786,10 +810,7 @@ decode_ddr3(const struct sysctlnode *nod
(s->sm_ddr3.ddr3_chipwidth + 2);
dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1);
- cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend +
- (s->sm_ddr3.ddr3_mtb_divisor / 2)) /
- s->sm_ddr3.ddr3_mtb_divisor;
- cycle_time *= s->sm_ddr3.ddr3_tCKmin;
+ cycle_time = __DDR3_VALUE_PICO(s, tCKmin);
bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3);
decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE,
"PC3", 0);
@@ -802,12 +823,15 @@ decode_ddr3(const struct sysctlnode *nod
s->sm_ddr3.ddr3_physbanks + 1,
cycle_time/1000, cycle_time % 1000);
-#define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin)
+#define __DDR3_CYCLES(val) \
+ ((val / cycle_time) + ((val % cycle_time) ? 1 : 0))
- aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin),
- __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin),
+ aprint_verbose_dev(self, LATENCY,
+ __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tAAmin)),
+ __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRCDmin)),
+ __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRPmin)),
(s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) /
- s->sm_ddr3.ddr3_tCKmin);
+ s->sm_ddr3.ddr3_tCKmin_mtb);
#undef __DDR3_CYCLES
Index: src/sys/dev/ic/spdmemvar.h
diff -u src/sys/dev/ic/spdmemvar.h:1.14 src/sys/dev/ic/spdmemvar.h:1.15
--- src/sys/dev/ic/spdmemvar.h:1.14 Thu Dec 27 02:54:00 2018
+++ src/sys/dev/ic/spdmemvar.h Tue Mar 24 03:45:25 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: spdmemvar.h,v 1.14 2018/12/27 02:54:00 msaitoh Exp $ */
+/* $NetBSD: spdmemvar.h,v 1.15 2020/03/24 03:45:25 msaitoh Exp $ */
/*
* Copyright (c) 2007 Paul Goyette
@@ -463,20 +463,20 @@ struct spdmem_ddr3 { /* Dual Data Rat
);
uint8_t ddr3_mtb_dividend; /* 0x0108 = 0.1250ns */
uint8_t ddr3_mtb_divisor; /* 0x010f = 0.0625ns */
- uint8_t ddr3_tCKmin; /* in terms of mtb */
+ uint8_t ddr3_tCKmin_mtb;
uint8_t ddr3_unused3;
uint16_t ddr3_CAS_sup; /* Bit 0 ==> CAS 4 cycles */
- uint8_t ddr3_tAAmin; /* in terms of mtb */
+ uint8_t ddr3_tAAmin_mtb;
uint8_t ddr3_tWRmin;
- uint8_t ddr3_tRCDmin;
+ uint8_t ddr3_tRCDmin_mtb;
uint8_t ddr3_tRRDmin;
- uint8_t ddr3_tRPmin;
+ uint8_t ddr3_tRPmin_mtb;
SPD_BITFIELD( \
uint8_t ddr3_tRAS_msb:4, \
- uint8_t ddr3_tRC_msb:4, , \
+ uint8_t ddr3_tRCmin_mtb_msb:4, , \
);
uint8_t ddr3_tRAS_lsb;
- uint8_t ddr3_tRC_lsb;
+ uint8_t ddr3_tRCmin_mtb_lsb;
uint8_t ddr3_tRFCmin_lsb;
uint8_t ddr3_tRFCmin_msb;
uint8_t ddr3_tWTRmin;
@@ -502,7 +502,14 @@ struct spdmem_ddr3 { /* Dual Data Rat
uint8_t ddr3_non_std_devtype:7, \
uint8_t ddr3_std_device:1, , \
);
- uint8_t ddr3_unused4[26];
+ uint8_t ddr3_tCKmin_ftb;
+ uint8_t ddr3_tAAmin_ftb;
+ uint8_t ddr3_tRCDmin_ftb;
+ uint8_t ddr3_tRPmin_ftb;
+ uint8_t ddr3_tRCmin_ftb;
+ uint8_t ddr3_unused4[2];
+ uint8_t ddr3_MAC;
+ uint8_t ddr3_unused4a[17];
uint8_t ddr3_mod_height;
uint8_t ddr3_mod_thickness;
uint8_t ddr3_ref_card;
