Module Name: src
Committed By: martin
Date: Tue Apr 14 18:11:35 UTC 2020
Modified Files:
src/sys/dev/mii [netbsd-8]: miidevs.h miidevs_data.h
Log Message:
Regen for ticket #1529
To generate a diff of this commit:
cvs rdiff -u -r1.128.6.8 -r1.128.6.9 src/sys/dev/mii/miidevs.h
cvs rdiff -u -r1.116.6.8 -r1.116.6.9 src/sys/dev/mii/miidevs_data.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/miidevs.h
diff -u src/sys/dev/mii/miidevs.h:1.128.6.8 src/sys/dev/mii/miidevs.h:1.128.6.9
--- src/sys/dev/mii/miidevs.h:1.128.6.8 Mon Nov 25 15:57:49 2019
+++ src/sys/dev/mii/miidevs.h Tue Apr 14 18:11:35 2020
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs.h,v 1.128.6.8 2019/11/25 15:57:49 martin Exp $ */
+/* $NetBSD: miidevs.h,v 1.128.6.9 2020/04/14 18:11:35 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.125.6.8 2019/11/25 15:57:23 martin Exp
+ * NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
*/
/*-
@@ -60,10 +60,12 @@
#define MII_OUI_TRIDIUM 0x0001f0 /* Tridium */
#define MII_OUI_DATATRACK 0x0002c6 /* Data Track Technology */
#define MII_OUI_AGERE 0x00053d /* Agere */
+#define MII_OUI_QUAKE 0x000897 /* Quake Technologies */
#define MII_OUI_BANKSPEED 0x0006b8 /* Bankspeed Pty */
#define MII_OUI_NETEXCELL 0x0008bb /* NetExcell */
#define MII_OUI_NETAS 0x0009c3 /* Netas */
#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
+#define MII_OUI_AELUROS 0x000b25 /* Aeluros */
#define MII_OUI_RALINK 0x000c43 /* Ralink Technology */
#define MII_OUI_ASIX 0x000ec6 /* ASIX */
#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
@@ -71,13 +73,11 @@
#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
#define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */
#define MII_OUI_SUNPLUS 0x001105 /* Sunplus Technology */
-#define MII_OUI_ATHEROS 0x001374 /* Atheros */
#define MII_OUI_TERANETICS 0x0014a6 /* Teranetics */
#define MII_OUI_RALINK2 0x0017a5 /* Ralink Technology */
#define MII_OUI_AQUANTIA 0x0017b6 /* Aquantia Corporation */
#define MII_OUI_BROADCOM3 0x001be9 /* Broadcom Corporation */
#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
-#define MII_OUI_VIA 0x004063 /* VIA Technologies */
#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
#define MII_OUI_AMLOGIC 0x006051 /* Amlogic */
@@ -89,7 +89,6 @@
#define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
#define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */
#define MII_OUI_ATTANSIC 0x00c82e /* Attansic Technology */
-#define MII_OUI_RDC 0x00d02d /* RDC Semiconductor */
#define MII_OUI_JMICRON 0x00d831 /* JMicron */
#define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */
#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
@@ -104,6 +103,7 @@
/* Unregistered or wrong OUI */
#define MII_OUI_yyREALTEK 0x000004 /* Realtek */
#define MII_OUI_yyAMD 0x000058 /* Advanced Micro Devices */
+#define MII_OUI_xxVIA 0x0002c6 /* VIA Technologies */
#define MII_OUI_xxMYSON 0x00032d /* Myson Technology */
#define MII_OUI_xxTSC 0x00039c /* TDK Semiconductor */
#define MII_OUI_xxASIX 0x000674 /* Asix Semiconductor */
@@ -122,6 +122,7 @@
#define MII_OUI_xxVITESSE 0x008083 /* Vitesse Semiconductor */
#define MII_OUI_xxPMCSIERRA2 0x009057 /* PMC-Sierra */
#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
+#define MII_OUI_xxRDC 0x00d02d /* RDC Semiconductor */
#define MII_OUI_xxNATSEMI 0x1000e8 /* National Semiconductor */
#define MII_OUI_xxLEVEL1 0x782000 /* Level 1 */
#define MII_OUI_xxXAQTI 0xace000 /* XaQti Corp. */
@@ -133,8 +134,10 @@
/*
* Agere PHYs
*/
-#define MII_MODEL_AGERE_ET1011 0x0004
-#define MII_STR_AGERE_ET1011 "Agere ET1011 10/100/1000baseT PHY"
+#define MII_MODEL_AGERE_ET1011 0x0001
+#define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY"
+#define MII_MODEL_AGERE_ET1011C 0x0004
+#define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
/* Asix semiconductor PHYs */
#define MII_MODEL_xxASIX_AX88X9X 0x0031
@@ -166,13 +169,7 @@
#define MII_MODEL_xxAMLOGIC_GXL 0x0000
#define MII_STR_xxAMLOGIC_GXL "Meson GXL internal PHY"
-/* Atheros PHYs */
-#define MII_MODEL_ATHEROS_F1 0x0001
-#define MII_STR_ATHEROS_F1 "F1 10/100/1000 PHY"
-#define MII_MODEL_ATHEROS_F2 0x0002
-#define MII_STR_ATHEROS_F2 "F2 10/100 PHY"
-
-/* Attansic PHYs */
+/* Attansic/Atheros PHYs */
#define MII_MODEL_ATTANSIC_L1 0x0001
#define MII_STR_ATTANSIC_L1 "L1 10/100/1000 PHY"
#define MII_MODEL_ATTANSIC_L2 0x0002
@@ -300,6 +297,8 @@
#define MII_STR_BROADCOM3_BCM53125 "BCM53125 1000BASE-T switch"
#define MII_MODEL_BROADCOM3_BCM5720C 0x0036
#define MII_STR_BROADCOM3_BCM5720C "BCM5720C 1000BASE-T media interface"
+#define MII_MODEL_BROADCOM4_BCM54213PE 0x000a
+#define MII_STR_BROADCOM4_BCM54213PE "BCM54213PE 1000BASE-T media interface"
#define MII_MODEL_BROADCOM4_BCM5725C 0x0038
#define MII_STR_BROADCOM4_BCM5725C "BCM5725C 1000BASE-T media interface"
#define MII_MODEL_xxBROADCOM_ALT1_BCM5906 0x0004
@@ -539,8 +538,12 @@
#define MII_STR_xxQUALSEMI_QS6612 "QS6612 10/100 media interface"
/* RDC Semiconductor PHYs */
-#define MII_MODEL_RDC_R6040 0x0003
-#define MII_STR_RDC_R6040 "R6040 10/100 media interface"
+#define MII_MODEL_xxRDC_R6040 0x0003
+#define MII_STR_xxRDC_R6040 "R6040 10/100 media interface"
+#define MII_MODEL_xxRDC_R6040_2 0x0005
+#define MII_STR_xxRDC_R6040_2 "R6040 10/100 media interface"
+#define MII_MODEL_xxRDC_R6040_3 0x0006
+#define MII_STR_xxRDC_R6040_3 "R6040 10/100 media interface"
/* RealTek PHYs */
#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
@@ -584,6 +587,10 @@
#define MII_MODEL_SMSC_LAN8742 0x0013
#define MII_STR_SMSC_LAN8742 "SMSC LAN8742 10/100 media interface"
+/* Teranetics PHY */
+#define MII_MODEL_TERANETICS_TN1010 0x0001
+#define MII_STR_TERANETICS_TN1010 "Teranetics TN1010 10GBase-T PHY"
+
/* Texas Instruments PHYs */
#define MII_MODEL_TI_TLAN10T 0x0001
#define MII_STR_TI_TLAN10T "ThunderLAN 10BASE-T media interface"
@@ -599,10 +606,10 @@
#define MII_STR_xxTSC_78Q2121 "78Q2121 100BASE-TX media interface"
/* VIA Technologies PHYs */
-#define MII_MODEL_VIA_VT6103 0x0032
-#define MII_STR_VIA_VT6103 "VT6103 10/100 PHY"
-#define MII_MODEL_VIA_VT6103_2 0x0034
-#define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY"
+#define MII_MODEL_xxVIA_VT6103 0x0032
+#define MII_STR_xxVIA_VT6103 "VT6103 10/100 PHY"
+#define MII_MODEL_xxVIA_VT6103_2 0x0034
+#define MII_STR_xxVIA_VT6103_2 "VT6103 10/100 PHY"
/* Vitesse PHYs (Now Microsemi) */
#define MII_MODEL_xxVITESSE_VSC8601 0x0002
Index: src/sys/dev/mii/miidevs_data.h
diff -u src/sys/dev/mii/miidevs_data.h:1.116.6.8 src/sys/dev/mii/miidevs_data.h:1.116.6.9
--- src/sys/dev/mii/miidevs_data.h:1.116.6.8 Mon Nov 25 15:57:49 2019
+++ src/sys/dev/mii/miidevs_data.h Tue Apr 14 18:11:35 2020
@@ -1,10 +1,10 @@
-/* $NetBSD: miidevs_data.h,v 1.116.6.8 2019/11/25 15:57:49 martin Exp $ */
+/* $NetBSD: miidevs_data.h,v 1.116.6.9 2020/04/14 18:11:35 martin Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: miidevs,v 1.125.6.8 2019/11/25 15:57:23 martin Exp
+ * NetBSD: miidevs,v 1.125.6.9 2020/04/14 17:57:17 martin Exp
*/
/*-
@@ -38,6 +38,7 @@
*/
struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_AGERE, MII_MODEL_AGERE_ET1011, MII_STR_AGERE_ET1011 },
+ { MII_OUI_AGERE, MII_MODEL_AGERE_ET1011C, MII_STR_AGERE_ET1011C },
{ MII_OUI_xxASIX, MII_MODEL_xxASIX_AX88X9X, MII_STR_xxASIX_AX88X9X },
{ MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772, MII_STR_yyASIX_AX88772 },
{ MII_OUI_yyASIX, MII_MODEL_yyASIX_AX88772A, MII_STR_yyASIX_AX88772A },
@@ -49,8 +50,6 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_ALTIMA, MII_MODEL_ALTIMA_Am79C874, MII_STR_ALTIMA_Am79C874 },
{ MII_OUI_AMLOGIC, MII_MODEL_AMLOGIC_GXL, MII_STR_AMLOGIC_GXL },
{ MII_OUI_xxAMLOGIC, MII_MODEL_xxAMLOGIC_GXL, MII_STR_xxAMLOGIC_GXL },
- { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, MII_STR_ATHEROS_F1 },
- { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2, MII_STR_ATHEROS_F2 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L1, MII_STR_ATTANSIC_L1 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_L2, MII_STR_ATTANSIC_L2 },
{ MII_OUI_ATTANSIC, MII_MODEL_ATTANSIC_AR8021, MII_STR_ATTANSIC_AR8021 },
@@ -112,6 +111,7 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, MII_STR_BROADCOM3_BCM57765 },
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM53125, MII_STR_BROADCOM3_BCM53125 },
{ MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, MII_STR_BROADCOM3_BCM5720C },
+ { MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM54213PE, MII_STR_BROADCOM4_BCM54213PE },
{ MII_OUI_BROADCOM4, MII_MODEL_BROADCOM4_BCM5725C, MII_STR_BROADCOM4_BCM5725C },
{ MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, MII_STR_xxBROADCOM_ALT1_BCM5906 },
{ MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CIS8201, MII_STR_xxCICADA_CIS8201 },
@@ -216,7 +216,9 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_xxPMCSIERRA2, MII_MODEL_xxPMCSIERRA2_PM8353, MII_STR_xxPMCSIERRA2_PM8353 },
{ MII_OUI_PMCSIERRA, MII_MODEL_PMCSIERRA_PM8354, MII_STR_PMCSIERRA_PM8354 },
{ MII_OUI_xxQUALSEMI, MII_MODEL_xxQUALSEMI_QS6612, MII_STR_xxQUALSEMI_QS6612 },
- { MII_OUI_RDC, MII_MODEL_RDC_R6040, MII_STR_RDC_R6040 },
+ { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040, MII_STR_xxRDC_R6040 },
+ { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040_2, MII_STR_xxRDC_R6040_2 },
+ { MII_OUI_xxRDC, MII_MODEL_xxRDC_R6040_3, MII_STR_xxRDC_R6040_3 },
{ MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, MII_STR_xxREALTEK_RTL8169S },
{ MII_OUI_yyREALTEK, MII_MODEL_yyREALTEK_RTL8201L, MII_STR_yyREALTEK_RTL8201L },
{ MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, MII_STR_REALTEK_RTL8251 },
@@ -234,13 +236,14 @@ struct mii_knowndev mii_knowndevs[] = {
{ MII_OUI_SMSC, MII_MODEL_SMSC_LAN8740, MII_STR_SMSC_LAN8740 },
{ MII_OUI_SMSC, MII_MODEL_SMSC_LAN8741A, MII_STR_SMSC_LAN8741A },
{ MII_OUI_SMSC, MII_MODEL_SMSC_LAN8742, MII_STR_SMSC_LAN8742 },
+ { MII_OUI_TERANETICS, MII_MODEL_TERANETICS_TN1010, MII_STR_TERANETICS_TN1010 },
{ MII_OUI_TI, MII_MODEL_TI_TLAN10T, MII_STR_TI_TLAN10T },
{ MII_OUI_TI, MII_MODEL_TI_100VGPMI, MII_STR_TI_100VGPMI },
{ MII_OUI_TI, MII_MODEL_TI_TNETE2101, MII_STR_TI_TNETE2101 },
{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2120, MII_STR_xxTSC_78Q2120 },
{ MII_OUI_xxTSC, MII_MODEL_xxTSC_78Q2121, MII_STR_xxTSC_78Q2121 },
- { MII_OUI_VIA, MII_MODEL_VIA_VT6103, MII_STR_VIA_VT6103 },
- { MII_OUI_VIA, MII_MODEL_VIA_VT6103_2, MII_STR_VIA_VT6103_2 },
+ { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103, MII_STR_xxVIA_VT6103 },
+ { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103_2, MII_STR_xxVIA_VT6103_2 },
{ MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8601, MII_STR_xxVITESSE_VSC8601 },
{ MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8641, MII_STR_xxVITESSE_VSC8641 },
{ MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8501, MII_STR_xxVITESSE_VSC8501 },
