Module Name: src
Committed By: martin
Date: Thu May 21 10:52:58 UTC 2020
Modified Files:
src/sys/dev/nvmm [netbsd-9]: nvmm.c
src/sys/dev/nvmm/x86 [netbsd-9]: nvmm_x86.c nvmm_x86_svm.c
nvmm_x86_vmx.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #919):
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.9
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.60
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.61
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.56
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.57
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.58
sys/dev/nvmm/nvmm.c: revision 1.29
Improve the CPUID emulation of basic leaves:
- Hide DCA and PQM, they cannot be used in guests.
- On Intel, explicitly handle each basic leaf until 0x16.
- On AMD, explicitly handle each basic leaf until 0x0D.
Respect the convention for the hypervisor information: return the highest
hypervisor leaf in 0x40000000.EAX.
Improve the CPUID emulation on nvmm-intel: limit the highest basic and
hypervisor leaves.
Complete rev1.26: reset nvmm_impl to NULL in nvmm_fini().
To generate a diff of this commit:
cvs rdiff -u -r1.22.2.3 -r1.22.2.4 src/sys/dev/nvmm/nvmm.c
cvs rdiff -u -r1.7.4.1 -r1.7.4.2 src/sys/dev/nvmm/x86/nvmm_x86.c
cvs rdiff -u -r1.46.4.4 -r1.46.4.5 src/sys/dev/nvmm/x86/nvmm_x86_svm.c
cvs rdiff -u -r1.36.2.6 -r1.36.2.7 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/nvmm/nvmm.c
diff -u src/sys/dev/nvmm/nvmm.c:1.22.2.3 src/sys/dev/nvmm/nvmm.c:1.22.2.4
--- src/sys/dev/nvmm/nvmm.c:1.22.2.3 Wed May 13 12:21:56 2020
+++ src/sys/dev/nvmm/nvmm.c Thu May 21 10:52:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm.c,v 1.22.2.3 2020/05/13 12:21:56 martin Exp $ */
+/* $NetBSD: nvmm.c,v 1.22.2.4 2020/05/21 10:52:58 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm.c,v 1.22.2.3 2020/05/13 12:21:56 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm.c,v 1.22.2.4 2020/05/21 10:52:58 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -998,6 +998,7 @@ nvmm_fini(void)
}
(*nvmm_impl->fini)();
+ nvmm_impl = NULL;
}
/* -------------------------------------------------------------------------- */
Index: src/sys/dev/nvmm/x86/nvmm_x86.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.1 src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.2
--- src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.1 Sat Nov 16 20:08:45 2019
+++ src/sys/dev/nvmm/x86/nvmm_x86.c Thu May 21 10:52:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86.c,v 1.7.4.1 2019/11/16 20:08:45 martin Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.7.4.2 2020/05/21 10:52:58 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.1 2019/11/16 20:08:45 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.2 2020/05/21 10:52:58 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -233,18 +233,18 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
.eax = ~0,
.ebx = ~0,
.ecx =
- /* Excluded: MONITOR, VMX, SMX, EST, TM2, PDCM, PCID, X2APIC,
+ /* Excluded: MONITOR, VMX, SMX, EST, TM2, PDCM, PCID, DCA, X2APIC,
* DEADLINE, RAZ. */
CPUID2_SSE3 | CPUID2_PCLMUL |
CPUID2_DTES64 | CPUID2_DS_CPL |
CPUID2_SSSE3 | CPUID2_CID |
CPUID2_SDBG | CPUID2_FMA |
CPUID2_CX16 | CPUID2_xTPR |
- CPUID2_DCA | CPUID2_SSE41 |
- CPUID2_SSE42 | CPUID2_MOVBE |
- CPUID2_POPCNT | CPUID2_AES |
- CPUID2_XSAVE | CPUID2_OSXSAVE |
- CPUID2_F16C | CPUID2_RDRAND,
+ CPUID2_SSE41 | CPUID2_SSE42 |
+ CPUID2_MOVBE | CPUID2_POPCNT |
+ CPUID2_AES | CPUID2_XSAVE |
+ CPUID2_OSXSAVE | CPUID2_F16C |
+ CPUID2_RDRAND,
.edx =
/* Excluded: MCE, MTRR, MCA, DS, ACPI, TM. */
CPUID_FPU | CPUID_VME |
@@ -265,16 +265,16 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = {
.eax = ~0,
.ebx =
- /* Excluded: TSC_ADJUST, AVX2, INVPCID, AVX512*, PT, SHA. */
+ /* Excluded: TSC_ADJUST, AVX2, INVPCID, QM, AVX512*, PT, SHA. */
CPUID_SEF_FSGSBASE |
CPUID_SEF_SGX | CPUID_SEF_BMI1 |
CPUID_SEF_HLE | CPUID_SEF_FDPEXONLY |
CPUID_SEF_SMEP | CPUID_SEF_BMI2 |
CPUID_SEF_ERMS | CPUID_SEF_RTM |
- CPUID_SEF_QM | CPUID_SEF_FPUCSDS |
- CPUID_SEF_PQE | CPUID_SEF_RDSEED |
- CPUID_SEF_ADX | CPUID_SEF_SMAP |
- CPUID_SEF_CLFLUSHOPT | CPUID_SEF_CLWB,
+ CPUID_SEF_FPUCSDS | CPUID_SEF_PQE |
+ CPUID_SEF_RDSEED | CPUID_SEF_ADX |
+ CPUID_SEF_SMAP | CPUID_SEF_CLFLUSHOPT |
+ CPUID_SEF_CLWB,
.ecx =
/* Excluded: AVX512*, MAWAU, RDPID. */
CPUID_SEF_PREFETCHWT1 | CPUID_SEF_UMIP |
Index: src/sys/dev/nvmm/x86/nvmm_x86_svm.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.4 src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.5
--- src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.4 Wed May 13 12:21:56 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_svm.c Thu May 21 10:52:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.4 2020/05/13 12:21:56 martin Exp $ */
+/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.5 2020/05/21 10:52:58 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.4 2020/05/13 12:21:56 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.5 2020/05/21 10:52:58 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -773,6 +773,8 @@ svm_inkernel_advance(struct vmcb *vmcb)
vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW;
}
+#define SVM_CPUID_MAX_HYPERVISOR 0x40000000
+
static void
svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx)
{
@@ -798,20 +800,33 @@ svm_inkernel_handle_cpuid(struct nvmm_cp
cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE;
}
break;
- case 0x00000005:
- case 0x00000006:
+ case 0x00000002: /* Empty */
+ case 0x00000003: /* Empty */
+ case 0x00000004: /* Empty */
+ case 0x00000005: /* Monitor/MWait */
+ case 0x00000006: /* Power Management Related Features */
cpudata->vmcb->state.rax = 0;
cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
break;
- case 0x00000007:
+ case 0x00000007: /* Structured Extended Features */
cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax;
cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx;
cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx;
cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx;
break;
- case 0x0000000D:
+ case 0x00000008: /* Empty */
+ case 0x00000009: /* Empty */
+ case 0x0000000A: /* Empty */
+ case 0x0000000B: /* Empty */
+ case 0x0000000C: /* Empty */
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x0000000D: /* Processor Extended State Enumeration */
if (svm_xcr0_mask == 0) {
break;
}
@@ -843,7 +858,9 @@ svm_inkernel_handle_cpuid(struct nvmm_cp
break;
}
break;
- case 0x40000000:
+
+ case 0x40000000: /* Hypervisor Information */
+ cpudata->vmcb->state.rax = SVM_CPUID_MAX_HYPERVISOR;
cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
@@ -851,6 +868,7 @@ svm_inkernel_handle_cpuid(struct nvmm_cp
memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4);
memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4);
break;
+
case 0x80000001:
cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax;
cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx;
Index: src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.6 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.7
--- src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.6 Wed May 13 12:21:56 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_vmx.c Thu May 21 10:52:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.6 2020/05/13 12:21:56 martin Exp $ */
+/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.7 2020/05/21 10:52:58 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.6 2020/05/13 12:21:56 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.7 2020/05/21 10:52:58 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1137,6 +1137,23 @@ error:
vmx_exit_invalid(exit, VMCS_EXITCODE_EXC_NMI);
}
+#define VMX_CPUID_MAX_BASIC 0x16
+#define VMX_CPUID_MAX_HYPERVISOR 0x40000000
+#define VMX_CPUID_MAX_EXTENDED 0x80000008
+static uint32_t vmx_cpuid_max_basic __read_mostly;
+
+static void
+vmx_inkernel_exec_cpuid(struct vmx_cpudata *cpudata, uint64_t eax, uint64_t ecx)
+{
+ u_int descs[4];
+
+ x86_cpuid2(eax, ecx, descs);
+ cpudata->gprs[NVMM_X64_GPR_RAX] = descs[0];
+ cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1];
+ cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2];
+ cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3];
+}
+
static void
vmx_inkernel_handle_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu,
uint64_t eax, uint64_t ecx)
@@ -1145,7 +1162,22 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
unsigned int ncpus;
uint64_t cr4;
+ if (eax < 0x40000000) {
+ if (__predict_false(eax > vmx_cpuid_max_basic)) {
+ eax = vmx_cpuid_max_basic;
+ vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
+ }
+ } else if (eax < 0x80000000) {
+ if (__predict_false(eax > VMX_CPUID_MAX_HYPERVISOR)) {
+ eax = vmx_cpuid_max_basic;
+ vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
+ }
+ }
+
switch (eax) {
+ case 0x00000000:
+ cpudata->gprs[NVMM_X64_GPR_RAX] = vmx_cpuid_max_basic;
+ break;
case 0x00000001:
cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_00000001.eax;
@@ -1167,14 +1199,24 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE;
}
break;
- case 0x00000005:
- case 0x00000006:
+ case 0x00000002:
+ break;
+ case 0x00000003:
+ cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x00000004: /* Deterministic Cache Parameters */
+ break; /* TODO? */
+ case 0x00000005: /* MONITOR/MWAIT */
+ case 0x00000006: /* Thermal and Power Management */
cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
break;
- case 0x00000007:
+ case 0x00000007: /* Structured Extended Feature Flags Enumeration */
cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_00000007.eax;
cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx;
cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx;
@@ -1183,13 +1225,20 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
cpudata->gprs[NVMM_X64_GPR_RBX] |= CPUID_SEF_INVPCID;
}
break;
- case 0x0000000A:
+ case 0x00000008: /* Empty */
+ case 0x00000009: /* Direct Cache Access Information */
cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
break;
- case 0x0000000B:
+ case 0x0000000A: /* Architectural Performance Monitoring */
+ cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x0000000B: /* Extended Topology Enumeration */
switch (ecx) {
case 0: /* Threads */
cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
@@ -1216,7 +1265,13 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
break;
}
break;
- case 0x0000000D:
+ case 0x0000000C: /* Empty */
+ cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x0000000D: /* Processor Extended State Enumeration */
if (vmx_xcr0_mask == 0) {
break;
}
@@ -1248,7 +1303,29 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
break;
}
break;
- case 0x40000000:
+ case 0x0000000E: /* Empty */
+ case 0x0000000F: /* Intel RDT Monitoring Enumeration */
+ case 0x00000010: /* Intel RDT Allocation Enumeration */
+ cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x00000011: /* Empty */
+ case 0x00000012: /* Intel SGX Capability Enumeration */
+ case 0x00000013: /* Empty */
+ case 0x00000014: /* Intel Processor Trace Enumeration */
+ cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x00000015: /* TSC and Nominal Core Crystal Clock Information */
+ case 0x00000016: /* Processor Frequency Information */
+ break;
+
+ case 0x40000000: /* Hypervisor Information */
+ cpudata->gprs[NVMM_X64_GPR_RAX] = VMX_CPUID_MAX_HYPERVISOR;
cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
@@ -1256,12 +1333,22 @@ vmx_inkernel_handle_cpuid(struct nvmm_ma
memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4);
memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4);
break;
+
case 0x80000001:
cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_80000001.eax;
cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx;
cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx;
cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx;
break;
+ case 0x80000002: /* Processor Brand String */
+ case 0x80000003: /* Processor Brand String */
+ case 0x80000004: /* Processor Brand String */
+ case 0x80000005: /* Reserved Zero */
+ case 0x80000006: /* Cache Information */
+ case 0x80000007: /* TSC Information */
+ case 0x80000008: /* Address Sizes */
+ break;
+
default:
break;
}
@@ -1285,18 +1372,11 @@ vmx_exit_cpuid(struct nvmm_machine *mach
struct vmx_cpudata *cpudata = vcpu->cpudata;
struct nvmm_vcpu_conf_cpuid *cpuid;
uint64_t eax, ecx;
- u_int descs[4];
size_t i;
eax = cpudata->gprs[NVMM_X64_GPR_RAX];
ecx = cpudata->gprs[NVMM_X64_GPR_RCX];
- x86_cpuid2(eax, ecx, descs);
-
- cpudata->gprs[NVMM_X64_GPR_RAX] = descs[0];
- cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1];
- cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2];
- cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3];
-
+ vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
vmx_inkernel_handle_cpuid(mach, vcpu, eax, ecx);
for (i = 0; i < VMX_NCPUIDS; i++) {
@@ -3238,6 +3318,9 @@ vmx_init(void)
/* Init the XCR0 mask. */
vmx_xcr0_mask = VMX_XCR0_MASK_DEFAULT & x86_xsave_features;
+ /* Init the max CPUID leaves. */
+ vmx_cpuid_max_basic = uimin(cpuid_level, VMX_CPUID_MAX_BASIC);
+
/* Init the TLB flush op, the EPT flush op and the EPTP type. */
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
if ((msr & IA32_VMX_EPT_VPID_INVVPID_CONTEXT) != 0) {
