Module Name: src
Committed By: jmcneill
Date: Wed Jun 3 18:26:06 UTC 2020
Modified Files:
src/sys/arch/arm/ti: ti_dpll_clock.c
Log Message:
Fix dpll clock setting on am335x
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/ti/ti_dpll_clock.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/ti/ti_dpll_clock.c
diff -u src/sys/arch/arm/ti/ti_dpll_clock.c:1.2 src/sys/arch/arm/ti/ti_dpll_clock.c:1.3
--- src/sys/arch/arm/ti/ti_dpll_clock.c:1.2 Tue Oct 29 22:19:13 2019
+++ src/sys/arch/arm/ti/ti_dpll_clock.c Wed Jun 3 18:26:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ti_dpll_clock.c,v 1.2 2019/10/29 22:19:13 jmcneill Exp $ */
+/* $NetBSD: ti_dpll_clock.c,v 1.3 2020/06/03 18:26:06 jmcneill Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ti_dpll_clock.c,v 1.2 2019/10/29 22:19:13 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ti_dpll_clock.c,v 1.3 2020/06/03 18:26:06 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -267,7 +267,7 @@ am3_dpll_clock_set_rate(void *priv, stru
control |= __SHIFTIN(AM3_DPLL_EN_NM_BYPASS, AM3_DPLL_EN);
WR4(sc, REG_CONTROL, control);
- while ((RD4(sc, REG_IDLEST) & AM3_ST_MN_BYPASS) != 0)
+ while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS)
;
mult_div1 = __SHIFTIN(mult, DPLL_MULT);
@@ -278,7 +278,7 @@ am3_dpll_clock_set_rate(void *priv, stru
control |= __SHIFTIN(AM3_DPLL_EN_LOCK, AM3_DPLL_EN);
WR4(sc, REG_CONTROL, control);
- while ((RD4(sc, REG_IDLEST) & AM3_ST_DPLL_CLK) != 0)
+ while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK)
;
return 0;
