Module Name: src
Committed By: simonb
Date: Sat Jun 13 14:41:24 UTC 2020
Modified Files:
src/sys/arch/mips/include: mipsNN.h
Log Message:
Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
among the other config3 register definitions.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/include/mipsNN.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.7 src/sys/arch/mips/include/mipsNN.h:1.8
--- src/sys/arch/mips/include/mipsNN.h:1.7 Sat Jun 13 14:39:07 2020
+++ src/sys/arch/mips/include/mipsNN.h Sat Jun 13 14:41:24 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsNN.h,v 1.7 2020/06/13 14:39:07 simonb Exp $ */
+/* $NetBSD: mipsNN.h,v 1.8 2020/06/13 14:41:24 simonb Exp $ */
/*
* Copyright 2000, 2001
@@ -239,9 +239,6 @@
/* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */
#define MIPSNN_CFG3_CMGCR 0x20000000
-/* "ULRI" (R): UserLocal register is implemented. */
-#define MIPSNN_CFG3_ULRI 0x00002000
-
/* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */
#define MIPSNN_CFG3_IPLW_MASK 0x00600000
#define MIPSNN_CFG3_IPLW_SHIFT 21
@@ -271,6 +268,9 @@
#define MIPSNN_CFG3_ISA_MIPS64_OOR 2 /* both, MIPS64 out of reset */
#define MIPSNN_CFG3_ISA_microMIPS64_OOR 3 /* both, microMIPS64 OOR */
+/* "ULRI" (R): UserLocal register is implemented. */
+#define MIPSNN_CFG3_ULRI 0x00002000
+
/* "DSP2P" (R): DSP v2 ASE extension present. */
#define MIPSNN_CFG3_DSP2P 0x00000800
