Module Name: src
Committed By: martin
Date: Sat Jun 20 16:38:42 UTC 2020
Modified Files:
src/sys/arch/mips/include [netbsd-9]: cache_r5k.h
src/sys/arch/mips/mips [netbsd-9]: cache_r5k.c cache_r5k_subr.S
Log Message:
Pull up following revision(s) (requested by tsutsui in ticket #965):
sys/arch/mips/include/cache_r5k.h: revision 1.5
sys/arch/mips/mips/cache_r5k_subr.S: revision 1.4
sys/arch/mips/mips/cache_r5k.c: revision 1.21
Use proper "page" alignments for R5k Page Invalidate(S) op. PR/55139
According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."
This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops. Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.
While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.
No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.4.22.1 src/sys/arch/mips/include/cache_r5k.h
cvs rdiff -u -r1.20 -r1.20.14.1 src/sys/arch/mips/mips/cache_r5k.c
cvs rdiff -u -r1.3 -r1.3.60.1 src/sys/arch/mips/mips/cache_r5k_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cache_r5k.h
diff -u src/sys/arch/mips/include/cache_r5k.h:1.4 src/sys/arch/mips/include/cache_r5k.h:1.4.22.1
--- src/sys/arch/mips/include/cache_r5k.h:1.4 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_r5k.h Sat Jun 20 16:38:42 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5k.h,v 1.4 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_r5k.h,v 1.4.22.1 2020/06/20 16:38:42 martin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -61,3 +61,13 @@ void r5k_sdcache_inv_range(register_t, v
void r5k_sdcache_wb_range(register_t, vsize_t);
#endif /* _KERNEL && !_LOCORE */
+
+#define CACHEOP_R5K_Page_Invalidate_S 0x17
+
+#define R5K_SC_LINESIZE 32
+#define R5K_SC_PAGESIZE (R5K_SC_LINESIZE * 128)
+#define R5K_SC_PAGEMASK (R5K_SC_PAGESIZE - 1)
+
+#define mips_r5k_round_page(x) (((x) + (register_t)R5K_SC_PAGEMASK) \
+ & (register_t)R5K_SC_PAGEMASK)
+#define mips_r5k_trunc_page(x) ((x) & (register_t)R5K_SC_PAGEMASK)
Index: src/sys/arch/mips/mips/cache_r5k.c
diff -u src/sys/arch/mips/mips/cache_r5k.c:1.20 src/sys/arch/mips/mips/cache_r5k.c:1.20.14.1
--- src/sys/arch/mips/mips/cache_r5k.c:1.20 Thu Apr 27 20:05:09 2017
+++ src/sys/arch/mips/mips/cache_r5k.c Sat Jun 20 16:38:42 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5k.c,v 1.20 2017/04/27 20:05:09 skrll Exp $ */
+/* $NetBSD: cache_r5k.c,v 1.20.14.1 2020/06/20 16:38:42 martin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.20 2017/04/27 20:05:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.20.14.1 2020/06/20 16:38:42 martin Exp $");
#include <sys/param.h>
@@ -407,9 +407,6 @@ r4600v2_pdcache_wb_range_32(register_t v
__asm(".set mips3");
-#define R5K_Page_Invalidate_S 0x17
-CTASSERT(R5K_Page_Invalidate_S == (CACHEOP_R4K_HIT_WB_INV|CACHE_R4K_SD));
-
void
r5k_sdcache_wbinv_all(void)
{
@@ -431,9 +428,6 @@ r5k_sdcache_wbinv_range_index(vaddr_t va
r5k_sdcache_wbinv_range((intptr_t)va, size);
}
-#define mips_r5k_round_page(x) round_line(x, PAGE_SIZE)
-#define mips_r5k_trunc_page(x) trunc_line(x, PAGE_SIZE)
-
void
r5k_sdcache_wbinv_range(register_t va, vsize_t size)
{
@@ -448,8 +442,8 @@ r5k_sdcache_wbinv_range(register_t va, v
__asm volatile("mfc0 %0, $28" : "=r"(taglo));
__asm volatile("mtc0 $0, $28");
- for (; va < eva; va += (128 * 32)) {
- cache_op_r4k_line(va, CACHEOP_R4K_HIT_WB_INV|CACHE_R4K_SD);
+ for (; va < eva; va += R5K_SC_PAGESIZE) {
+ cache_op_r4k_line(va, CACHEOP_R5K_Page_Invalidate_S);
}
mips_cp0_status_write(ostatus);
Index: src/sys/arch/mips/mips/cache_r5k_subr.S
diff -u src/sys/arch/mips/mips/cache_r5k_subr.S:1.3 src/sys/arch/mips/mips/cache_r5k_subr.S:1.3.60.1
--- src/sys/arch/mips/mips/cache_r5k_subr.S:1.3 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/mips/cache_r5k_subr.S Sat Jun 20 16:38:42 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5k_subr.S,v 1.3 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: cache_r5k_subr.S,v 1.3.60.1 2020/06/20 16:38:42 martin Exp $ */
/*
* Redistribution and use in source and binary forms, with or without
@@ -65,8 +65,8 @@ LEAF_NOPROFILE(r5k_enable_sdcache)
nop
2:
- cache 0x17, 0(t1) # 0x17 == Page_Invalidate_SD
- PTR_ADDU t1, t1, 4096
+ cache CACHEOP_R5K_Page_Invalidate_S, 0(t1)
+ PTR_ADDU t1, t1, R5K_SC_PAGESIZE
sltu v0, t1, t2
bne v0, zero, 2b
