Module Name: src
Committed By: simonb
Date: Mon Jun 22 03:05:07 UTC 2020
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_asxreg.h octeon_bootbusreg.h
octeon_ciureg.h octeon_corereg.h octeon_fpareg.h octeon_gmxreg.h
octeon_gpioreg.h octeon_ipdreg.h octeon_mpireg.h octeon_pip.c
octeon_pipreg.h octeon_powreg.h octeon_rnmreg.h octeon_twsireg.h
octeon_usbcreg.h octeon_usbnreg.h
Log Message:
Remove unused snprintb format strings.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_asxreg.h \
src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h \
src/sys/arch/mips/cavium/dev/octeon_gpioreg.h \
src/sys/arch/mips/cavium/dev/octeon_usbcreg.h \
src/sys/arch/mips/cavium/dev/octeon_usbnreg.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/cavium/dev/octeon_ciureg.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/cavium/dev/octeon_corereg.h \
src/sys/arch/mips/cavium/dev/octeon_fpareg.h \
src/sys/arch/mips/cavium/dev/octeon_gmxreg.h \
src/sys/arch/mips/cavium/dev/octeon_ipdreg.h \
src/sys/arch/mips/cavium/dev/octeon_mpireg.h \
src/sys/arch/mips/cavium/dev/octeon_pipreg.h \
src/sys/arch/mips/cavium/dev/octeon_powreg.h \
src/sys/arch/mips/cavium/dev/octeon_twsireg.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/cavium/dev/octeon_pip.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_rnmreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/dev/octeon_asxreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_asxreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_asxreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_asxreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_asxreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_asxreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_asxreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -155,114 +155,4 @@
#define ASX0_GMII_RX_DAT_SET_63_5 0xffffffe0
#define ASX0_GMII_RX_DAT_SET_SETTING 0x0000001f
-/* ---- */
-
-#define ASX0_RX_PRT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x3d" "63_3\0" \
- "f\x00\x03" "PRT_EN\0"
-#define ASX0_TX_PRT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x3d" "63_3\0" \
- "f\x00\x03" "PRT_EN\0"
-#define ASX0_INT_REG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x0b\x35" "63_11\0" \
- "f\x08\x03" "TXPSH\0" \
- "b\x07" "7\0" \
- "f\x04\x03" "TXPOP\0" \
- "b\x03" "3\0" \
- "f\x00\x03" "OVRFLW\0"
-#define ASX0_INT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x0b\x35" "63_11\0" \
- "f\x08\x03" "TXPSH\0" \
- "b\x07" "7\0" \
- "f\x04\x03" "TXPOP\0" \
- "b\x03" "3\0" \
- "f\x00\x03" "OVRFLW\0"
-#define ASX0_RX_CLK_SET0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_RX_CLK_SET1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_RX_CLK_SET2_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_PRT_LOOP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x07\x39" "63_7\0" \
- "f\x04\x03" "EXT_LOOP\0" \
- "b\x03" "3\0" \
- "f\x00\x03" "PRT_LOOP\0"
-#define ASX0_TX_CLK_SET0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_TX_CLK_SET1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_TX_CLK_SET2_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_COMP_BYP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_TX_HI_WATER000_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_TX_HI_WATER001_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_TX_HI_WATER002_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define ASX0_GMII_RX_CLK_SET_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x05\x3b" "63_5\0" \
- "f\x00\x05" "SETTING\0"
-#define ASX0_GMII_RX_DAT_SET_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x05\x3b" "63_5\0" \
- "f\x00\x05" "SETTING\0"
-#define ASX0_MII_RX_DAT_SET_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-
#endif /* _OCTEON_ASXREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_bootbusreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_bootbusreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -116,21 +116,6 @@
#define MIO_BOOT_BIST_STAT_LOC UINT64_C(0x0000000000000002)
#define MIO_BOOT_BIST_STAT_NCBI UINT64_C(0x0000000000000001)
-/* ---- snprintb */
-
-#define MIO_BOOT_REG_CFGN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x24" "SAM\0" \
- "f\x22\x02" "WE_EXT\0" \
- "f\x20\x02" "OE_EXT\0" \
- "b\x1f" "EN\0" \
- "b\x1e" "OR\0" \
- "b\x1d" "ALE\0" \
- "b\x1c" "WIDTH\0" \
- "f\x10\x0c" "SIZE\0" \
- "f\x00\x10" "BASE\0"
#define MIO_BOOT_REG_CFG0_BITS MIO_BOOT_REG_CFGN_BITS
#define MIO_BOOT_REG_CFG1_BITS MIO_BOOT_REG_CFGN_BITS
#define MIO_BOOT_REG_CFG2_BITS MIO_BOOT_REG_CFGN_BITS
@@ -140,23 +125,6 @@
#define MIO_BOOT_REG_CFG6_BITS MIO_BOOT_REG_CFGN_BITS
#define MIO_BOOT_REG_CFG7_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_TIMN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3f" "PAGEM\0" \
- "b\x3e" "WAITM\0" \
- "f\x3c\x02" "PAGES\0" \
- "f\x36\x06" "ALE\0" \
- "f\x30\x06" "PAGE\0" \
- "f\x2a\x06" "WAIT\0" \
- "f\x24\x06" "PAUSE\0" \
- "f\x1e\x06" "WR_HLD\0" \
- "f\x18\x06" "RD_HLD\0" \
- "f\x12\x06" "WE\0" \
- "f\x0c\x06" "OE\0" \
- "f\x06\x06" "CE\0" \
- "f\x00\x06" "ADR\0"
#define MIO_BOOT_REG_TIM0_BITS MIO_BOOT_REG_TIMN_BITS
#define MIO_BOOT_REG_TIM1_BITS MIO_BOOT_REG_TIMN_BITS
#define MIO_BOOT_REG_TIM2_BITS MIO_BOOT_REG_TIMN_BITS
@@ -166,12 +134,6 @@
#define MIO_BOOT_REG_TIM6_BITS MIO_BOOT_REG_TIMN_BITS
#define MIO_BOOT_REG_TIM7_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_LOC_CFGN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "EN\0" \
- "f\x03\x19" "BASE\0"
#define MIO_BOOT_LOC_CFG0_BITS MIO_BOOT_LOC_CFGN_BITS
#define MIO_BOOT_LOC_CFG1_BITS MIO_BOOT_LOC_CFGN_BITS
#define MIO_BOOT_LOC_CFG2_BITS MIO_BOOT_LOC_CFGN_BITS
@@ -181,42 +143,6 @@
#define MIO_BOOT_LOC_CFG6_BITS MIO_BOOT_LOC_CFGN_BITS
#define MIO_BOOT_LOC_CFG7_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_ADR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x05" "ADR\0"
-
-#define MIO_BOOT_ERR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x01" "WAIT_ERR\0" \
- "b\x00" "ADR_ERR\0"
-
-#define MIO_BOOT_INT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x01" "WAIT_INT\0" \
- "b\x00" "ADR_INT\0"
-
-#define MIO_BOOT_THR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x08\x06" "FIF_CNT\0" \
- "f\x00\x06" "FIF_THR\0"
-
-#define MIO_BOOT_BIST_STAT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x03" "NCBO_1\0" \
- "b\x02" "NCBO_0\0" \
- "b\x01" "LOC\0" \
- "b\x00" "NCBI\0"
-
/* ---- bus_space */
#define MIO_BOOT_REG_CFG0_OFFSET 0x0000
Index: src/sys/arch/mips/cavium/dev/octeon_gpioreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_gpioreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_gpioreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_gpioreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_gpioreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gpioreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_gpioreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -74,19 +74,6 @@
/* XXX */
-/* ---- snprintb */
-
-#define GPIO_BIT_CFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x08\x04" "FIL_SEL\0" \
- "f\x04\x04" "FIL_CNT\0" \
- "b\x03" "INT_TYPE\0" \
- "b\x02" "INT_EN\0" \
- "b\x01" "RX_XOR\0" \
- "b\x00" "TX_OE\0"
-
/* ---- bus_space */
#define GPIO_BASE 0x0001070000000800ULL
Index: src/sys/arch/mips/cavium/dev/octeon_usbcreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_usbcreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_usbcreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_usbcreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_usbcreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_usbcreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_usbcreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -573,307 +573,6 @@
/* for USBC_NPTXDFIFO(0..7) */
#define USBC_NPTXDFIFOX_DATA 0xffffffff
-/* ---- snprintb */
-
-#define USBC_GOTGINT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x13" "DBNCEDONE\0" \
- "b\x12" "ADEVTOUTCHG\0" \
- "b\x11" "HSTNEGDET\0" \
- "b\x09" "HSTNEGSUCSTSCHNG\0" \
- "b\x08" "SESREQSUCSTSCHNG\0" \
- "b\x02" "SESENDDET\0"
-
-#define USBC_GINTSTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "WKUPINT\0" \
- "b\x1e" "SESSREQINT\0" \
- "b\x1d" "DISCONNINT\0" \
- "b\x1c" "CONIDSTSCHNG\0" \
- "b\x1a" "PTXFEMP\0" \
- "b\x19" "HCHINT\0" \
- "b\x18" "PRTINT\0" \
- "b\x16" "FETSUSP\0" \
- "b\x15" "INCOMPLP\0" \
- "b\x14" "INCOMPISOIN\0" \
- "b\x13" "OEPINT\0" \
- "b\x12" "IEPINT\0" \
- "b\x11" "EPMIS\0" \
- "b\x0f" "EOPF\0" \
- "b\x0e" "ISOOUTDROP\0" \
- "b\x0d" "ENUMDONE\0" \
- "b\x0c" "USBRST\0" \
- "b\x0b" "USBSUSP\0" \
- "b\x0a" "ERLYSUSP\0" \
- "b\x09" "I2CINT\0" \
- "b\x08" "ULPICKINT\0" \
- "b\x07" "GOUTNAKEFF\0" \
- "b\x06" "GINNAKEFF\0" \
- "b\x05" "NPTXFEMP\0" \
- "b\x04" "RXFLVL\0" \
- "b\x03" "SOF\0" \
- "b\x02" "OTGINT\0" \
- "b\x01" "MODEMIS\0" \
- "b\x00" "CURMOD\0"
-
-#define USBC_GINTMSK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "WKUPINTMSK\0" \
- "b\x1e" "SESSREQINTMSK\0" \
- "b\x1d" "DISCONNINTMSK\0" \
- "b\x1c" "CONIDSTSTCHNGMSK\0" \
- "b\x1a" "PTXFEMPMSK\0" \
- "b\x19" "HCHINTMSK\0" \
- "b\x18" "PRTINTMSK\0" \
- "b\x16" "FETSUSPMSK\0" \
- "b\x15" "INCOMPISOOUTMSK\0" \
- "b\x14" "INCOMPISOINMSK\0" \
- "b\x13" "OEPINTMSK\0" \
- "b\x12" "INEPINTMSK\0" \
- "b\x11" "EPMISMSK\0" \
- "b\x0f" "EOPFMSK\0" \
- "b\x0e" "ISOOUTDROPMSK\0" \
- "b\x0d" "ENUMDONEMSK\0" \
- "b\x0c" "USBRSTMSK\0" \
- "b\x0b" "USBSUSPMSK\0" \
- "b\x0a" "ERLYSUSPMSK\0" \
- "b\x09" "I2CINT\0" \
- "b\x08" "ULPICKINTMSK\0" \
- "b\x07" "GOUTNAKEFFMSK\0" \
- "b\x06" "GINNAKEFFMSK\0" \
- "b\x05" "NPTXFEMPMSK\0" \
- "b\x04" "RXFLVLMSK\0" \
- "b\x03" "SOFMSK\0" \
- "b\x02" "OTGINTMSK\0" \
- "b\x01" "MODEMISMSK\0"
-
-#define USBC_GRXSTSRH_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x11\x04" "PKTSTS\0" \
- "f\x0f\x02" "DPID\0" \
- "f\x04\x0b" "BCNT\0" \
- "f\x00\x04" "CHNUM\0"
-
-#define USBC_GRXSTSPH_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x11\x04" "PKTSTS\0" \
- "f\x0f\x02" "DPID\0" \
- "f\x04\x0b" "BCNT\0" \
- "f\x00\x04" "CHNUM\0"
-
-#define USBC_GUSBCFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x10" "OTGI2CSEL\0" \
- "b\x0f" "PHYLPWRCLKSEL\0" \
- "f\x0a\x04" "USBTRDTIM\0" \
- "b\x09" "HNPCAP\0" \
- "b\x08" "SRPCAP\0" \
- "b\x07" "DDRSEL\0" \
- "b\x06" "PHYSEL\0" \
- "b\x05" "FSINTF\0" \
- "b\x04" "ULPI_UTMI_SEL\0" \
- "b\x03" "PHYIF\0" \
- "f\x00\x03" "TOUTCAL\0"
-
-#define USBC_GRSTCTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "AHBIDLE\0" \
- "b\x1e" "DMAREQ\0" \
- "f\x06\x05" "TXFNUM\0" \
- "b\x05" "TXFFLSH\0" \
- "b\x04" "RXFFLSH\0" \
- "b\x03" "INTKNQFLSH\0" \
- "b\x02" "FRMCNTRRST\0" \
- "b\x01" "HSFTRST\0" \
- "b\x00" "CSFTRST\0"
-
-#define USBC_GAHBCFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x08" "PTXFEMPLVL\0" \
- "b\x07" "NPTXFEMPLVL\0" \
- "b\x05" "DMAEN\0" \
- "f\x01\x04" "HBSTLEN\0" \
- "b\x00" "GLBLINTRMSK\0"
-
-#define USBC_GRXFSIZ_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "RXFDEP\0"
-
-#define USBC_GNPTXFSIZ_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x10" "NPTXFEDP\0" \
- "f\x00\x10" "NPTXFSTADDR\0"
-
-#define USBC_GNPTXSTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1b\x04" "NPTXQTOP_CHNUM\0" \
- "f\x19\x02" "NPTXQTOP_ENTRY\0" \
- "b\x18" "NPTXQTOP_TERMINATE\0" \
- "f\x10\x08" "NPTXQSPCAVAIL\0" \
- "f\x00\x10" "NPTXFSPCAVAIL\0"
-
-#define USBC_GHWCFG1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "EPDIR\0"
-
-#define USBC_GHWCFG2_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1a\x05" "TKNQDEPTH\0" \
- "f\x18\x02" "PTXQDEPTH\0" \
- "f\x16\x02" "NPTXQDEPTH\0" \
- "b\x13" "DYNFIFOSIZING\0" \
- "b\x12" "PERIOSUPPORT\0" \
- "f\x0e\x04" "NUMHSTCHN1\0" \
- "f\x0a\x04" "NUMDEVEPS\0" \
- "f\x08\x02" "FSPHYTYPE\0" \
- "f\x06\x02" "HSPHYTYPE\0" \
- "b\x05" "SINGPNT\0" \
- "f\x03\x02" "OTGARCH\0" \
- "f\x00\x03" "OTGMODE\0"
-
-#define USBC_GHWCFG3_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x10" "DFIFODEPTH\0" \
- "b\x0c" "AHBPHYSYNC\0" \
- "b\x0b" "RSTTYPE\0" \
- "b\x0a" "OPTFEATURE\0" \
- "b\x09" "VENDOR_CONTROL_INTERFACE_SUPPORT\0" \
- "b\x08" "I2C_SELECTION\0" \
- "b\x07" "OTGEN\0" \
- "f\x04\x03" "PKTSIZEWIDTH\0" \
- "f\x00\x04" "XFERSIZEWIDTH\0"
-
-#define USBC_GHWCFG4_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x18" "SESSENDFLTR\0" \
- "b\x18" "BVAILDFLTR\0" \
- "b\x17" "AVAILDFLTR\0" \
- "b\x16" "VBUSVALIDFLTR\0" \
- "b\x15" "IDDGFLTR\0" \
- "f\x10\x04" "NUMCTLEPS\0" \
- "f\x0e\x02" "PHYDATAWIDTH\0" \
- "b\x05" "AHBFREQ\0" \
- "b\x04" "ENABLEPWROPT\0" \
- "f\x00\x04" "NUMDEVPERIOEPS\0"
-
-#define USBC_HCFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x02" "FSLSSUPP\0" \
- "f\x00\x02" "FSLSPCLKSEL\0"
-
-#define USBC_HPRT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x11\x02" "PRTSPD\0" \
- "f\x0d\x04" "PRTTSTCTL\0" \
- "b\x0c" "PRTPWR\0" \
- "f\x0a\x02" "PRTLNSTS\0" \
- "b\x08" "PRTRST\0" \
- "b\x07" "PRTSUSP\0" \
- "b\x06" "PRTRES\0" \
- "b\x05" "PRTOVRCURRCHNG\0" \
- "b\x04" "PRTOVRCURRACT\0" \
- "b\x03" "PRTENCHNG\0" \
- "b\x02" "PRTENA\0" \
- "b\x01" "PRTCONNDET\0" \
- "b\x00" "PRTCONNSTS\0"
-
-#define USBC_HFIR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "FRINT\0"
-
-#define USBC_HAINT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0f" "HAINT_F\0" \
- "b\x0e" "HAINT_E\0" \
- "b\x0d" "HAINT_D\0" \
- "b\x0c" "HAINT_C\0" \
- "b\x0b" "HAINT_B\0" \
- "b\x0a" "HAINT_A\0" \
- "b\x09" "HAINT_9\0" \
- "b\x08" "HAINT_8\0" \
- "b\x07" "HAINT_7\0" \
- "b\x06" "HAINT_6\0" \
- "b\x05" "HAINT_5\0" \
- "b\x04" "HAINT_4\0" \
- "b\x03" "HAINT_3\0" \
- "b\x02" "HAINT_2\0" \
- "b\x01" "HAINT_1\0" \
- "b\x00" "HAINT_0\0"
-
-#define USBC_HAINTMSK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0f" "HAINTMSK_F\0" \
- "b\x0e" "HAINTMSK_E\0" \
- "b\x0d" "HAINTMSK_D\0" \
- "b\x0c" "HAINTMSK_C\0" \
- "b\x0b" "HAINTMSK_B\0" \
- "b\x0a" "HAINTMSK_A\0" \
- "b\x09" "HAINTMSK_9\0" \
- "b\x08" "HAINTMSK_8\0" \
- "b\x07" "HAINTMSK_7\0" \
- "b\x06" "HAINTMSK_6\0" \
- "b\x05" "HAINTMSK_5\0" \
- "b\x04" "HAINTMSK_4\0" \
- "b\x03" "HAINTMSK_3\0" \
- "b\x02" "HAINTMSK_2\0" \
- "b\x01" "HAINTMSK_1\0" \
- "b\x00" "HAINTMSK_0\0"
-
-#define USBC_HCINTX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0a" "DATATGLERR\0" \
- "b\x09" "FRMOVRUN\0" \
- "b\x08" "BBLERR\0" \
- "b\x07" "XACTERR\0" \
- "b\x06" "NYET\0" \
- "b\x05" "ACK\0" \
- "b\x04" "NAK\0" \
- "b\x03" "STALL\0" \
- "b\x02" "AHBERR\0" \
- "b\x01" "CHHLTD\0" \
- "b\x00" "XFERCOMPL\0"
#define USBC_HCINT0_BITS USBC_HCINTX_BITS
#define USBC_HCINT1_BITS USBC_HCINTX_BITS
#define USBC_HCINT2_BITS USBC_HCINTX_BITS
@@ -883,21 +582,6 @@
#define USBC_HCINT6_BITS USBC_HCINTX_BITS
#define USBC_HCINT7_BITS USBC_HCINTX_BITS
-#define USBC_HCINTMSKX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0a" "DATATGLERRMSK\0" \
- "b\x09" "FRMOVRUNMSK\0" \
- "b\x08" "BBLERRMSK\0" \
- "b\x07" "XACTERRMSK\0" \
- "b\x06" "NYETMSK\0" \
- "b\x05" "ACKMSK\0" \
- "b\x04" "NAKMSK\0" \
- "b\x03" "STALLMSK\0" \
- "b\x02" "AHBERRMSK\0" \
- "b\x01" "CHHLTDMSK\0" \
- "b\x00" "XFERCOMPLMSK\0"
#define USBC_HCINTMSK0_BITS USBC_HCINTMSKX_BITS
#define USBC_HCINTMSK1_BITS USBC_HCINTMSKX_BITS
#define USBC_HCINTMSK2_BITS USBC_HCINTMSKX_BITS
@@ -907,20 +591,6 @@
#define USBC_HCINTMSK6_BITS USBC_HCINTMSKX_BITS
#define USBC_HCINTMSK7_BITS USBC_HCINTMSKX_BITS
-#define USBC_HCCHARX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "CHENA\0" \
- "b\x1e" "CHDIS\0" \
- "b\x1d" "ODDFRM\0" \
- "f\x16\x07" "DEVADDR\0" \
- "f\x14\x02" "EC\0" \
- "f\x12\x02" "EPTYPE\0" \
- "b\x11" "LSPDDEV\0" \
- "b\x0f" "EPDIR\0" \
- "f\x0b\x04" "EPNUM\0" \
- "f\x00\x0b" "MPS\0"
#define USBC_HCCHAR0_BITS USBC_HCCHARX_BITS
#define USBC_HCCHAR1_BITS USBC_HCCHARX_BITS
#define USBC_HCCHAR2_BITS USBC_HCCHARX_BITS
@@ -930,14 +600,6 @@
#define USBC_HCCHAR6_BITS USBC_HCCHARX_BITS
#define USBC_HCCHAR7_BITS USBC_HCCHARX_BITS
-#define USBC_HCTSIZX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "DOPNG\0" \
- "f\x1d\x02" "PID\0" \
- "f\x13\x0a" "PKTCNT\0" \
- "f\x00\x13" "XFERSIZE\0"
#define USBC_HCTSIZ0_BITS USBC_HCTSIZX_BITS
#define USBC_HCTSIZ1_BITS USBC_HCTSIZX_BITS
#define USBC_HCTSIZ2_BITS USBC_HCTSIZX_BITS
Index: src/sys/arch/mips/cavium/dev/octeon_usbnreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_usbnreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_usbnreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_usbnreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_usbnreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_usbnreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_usbnreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -198,143 +198,6 @@
#define USBN_DMA0_OUTB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000)
#define USBN_DMA0_OUTB_CHNX_ADDR UINT64_C(0x0000000fffffffff)
-/* ---- snprintb */
-
-#define USBN_INT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x25" "ND4O_DPF\0" \
- "b\x24" "ND4O_DPE\0" \
- "b\x23" "ND4O_RPF\0" \
- "b\x22" "ND4O_RPE\0" \
- "b\x21" "LTL_F_PF\0" \
- "b\x20" "LTL_F_PE\0" \
- "b\x1f" "U2N_C_PE\0" \
- "b\x1e" "U2N_C_PF\0" \
- "b\x1d" "U2N_D_PF\0" \
- "b\x1c" "U2N_D_PE\0" \
- "b\x1b" "N2U_PE\0" \
- "b\x1a" "N2U_PF\0" \
- "b\x19" "UOD_PF\0" \
- "b\x18" "UOD_PE\0" \
- "b\x17" "RQ_Q3_E\0" \
- "b\x16" "RQ_Q3_F\0" \
- "b\x15" "RQ_Q2_E\0" \
- "b\x14" "RQ_Q2_F\0" \
- "b\x13" "RG_FI_F\0" \
- "b\x12" "RG_FI_E\0" \
- "b\x11" "LT_FI_F\0" \
- "b\x10" "LT_FI_E\0" \
- "b\x0f" "L2C_A_F\0" \
- "b\x0e" "L2C_S_E\0" \
- "b\x0d" "DCRED_F\0" \
- "b\x0c" "DCRED_E\0" \
- "b\x0b" "LT_PU_F\0" \
- "b\x0a" "LT_PO_E\0" \
- "b\x09" "NT_PU_F\0" \
- "b\x08" "NT_PO_E\0" \
- "b\x07" "PT_PU_F\0" \
- "b\x06" "PT_PO_E\0" \
- "b\x05" "LR_PU_F\0" \
- "b\x04" "LR_PO_E\0" \
- "b\x03" "NR_PU_F\0" \
- "b\x02" "NR_PO_E\0" \
- "b\x01" "PR_PU_F\0" \
- "b\x00" "PR_PO_E\0"
-
-#define USBN_CLK_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x12\x02" "DIVIDE2\0" \
- "b\x11" "HCLK_RST\0" \
- "b\x10" "P_X_ON\0" \
- "b\x0f" "P_RCLK\0" \
- "f\x0e\x02" "P_RTYPE\0" \
- "b\x0e" "P_XENBN\0" \
- "b\x0d" "P_COM_ON\0" \
- "f\x0b\x02" "P_C_SEL\0" \
- "b\x0a" "CDIV_BYP\0" \
- "f\x08\x02" "SD_MODE\0" \
- "b\x07" "S_BIST\0" \
- "b\x06" "POR\0" \
- "b\x05" "ENABLE\0" \
- "b\x04" "PRST\0" \
- "b\x03" "HRST\0" \
- "f\x00\x03" "DIVIDE\0"
-
-#define USBN_USBP_CTL_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3f" "TXRISETUNE\0" \
- "f\x3b\x04" "TXVREFTUNE\0" \
- "f\x37\x04" "TXFSLSTUNE\0" \
- "f\x35\x02" "TXHSXVTUNE\0" \
- "f\x32\x03" "SQRXTUNE\0" \
- "f\x2f\x03" "COMPDISTUNE\0" \
- "f\x2c\x03" "OTGTUNE\0" \
- "b\x2b" "OTGDISABLE\0" \
- "b\x2a" "PORTRESET\0" \
- "b\x29" "DRVVBUS\0" \
- "b\x28" "LSBIST\0" \
- "b\x27" "FSBIST\0" \
- "b\x26" "HSBIST\0" \
- "b\x25" "BIST_DONE\0" \
- "b\x24" "BIST_ERR\0" \
- "f\x20\x04" "TDATA_OUT\0" \
- "f\x1d\x03" "SPARES\0" \
- "b\x1c" "USBC_END\0" \
- "b\x1b" "USBP_BIST\0" \
- "b\x1a" "TCLK\0" \
- "b\x19" "DP_PULLD\0" \
- "b\x18" "DM_PULLD\0" \
- "b\x17" "HST_MODE\0" \
- "f\x13\x04" "TUNING\0" \
- "b\x12" "TX_BS_ENH\0" \
- "b\x11" "TX_BS_EN\0" \
- "b\x10" "LOOP_ENB\0" \
- "b\x0f" "VTEST_ENB\0" \
- "b\x0e" "BIST_ENB\0" \
- "b\x0d" "TDATA_SEL\0" \
- "f\x09\x04" "TADDR_IN\0" \
- "f\x01\x08" "TDATA_IN\0" \
- "b\x00" "ATE_RESET\0"
-
-#define USBN_BIST_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x06" "U2NC_BIS\0" \
- "b\x05" "U2NF_BIS\0" \
- "b\x04" "E2HC_BIS\0" \
- "b\x03" "N2UF_BIS\0" \
- "b\x02" "USBC_BIS\0" \
- "b\x01" "NIF_BIS\0" \
- "b\x00" "NOF_BIS\0"
-
-#define USBN_CTL_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x05" "DMA_0PAG\0" \
- "b\x04" "DMA_STT\0" \
- "b\x03" "DMA_TEST\0" \
- "b\x02" "INV_A2\0" \
- "f\x00\x02" "L2C_EMOD\0"
-
-#define USBN_DMA_TEST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x27" "DONE\0" \
- "b\x26" "REQ\0" \
- "f\x14\x12" "F_ADDR\0" \
- "f\x09\x0b" "COUNT\0" \
- "f\x04\x05" "CHANNEL\0" \
- "f\x00\x04" "BURST\0"
-
/* ---- bus_space */
#define USBN_NUNITS 1
Index: src/sys/arch/mips/cavium/dev/octeon_ciureg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.7 src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.8
--- src/sys/arch/mips/cavium/dev/octeon_ciureg.h:1.7 Fri Jun 19 02:23:43 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ciureg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ciureg.h,v 1.7 2020/06/19 02:23:43 simonb Exp $ */
+/* $NetBSD: octeon_ciureg.h,v 1.8 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -263,290 +263,42 @@
#define CIU_PCI_INTA_XXX_63_2 UINT64_C(0xfffffffffffffffc)
#define CIU_PCI_INTA_INT UINT64_C(0x0000000000000003)
-/* -- snprintb(9) */
-
-#define CIU_INTX_SUM0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3a" "MPI\0" \
- "b\x39" "PCM\0" \
- "b\x38" "USB\0" \
- "b\x37" "TIMER_3\0" \
- "b\x36" "TIMER_2\0" \
- "b\x35" "TIMER_1\0" \
- "b\x34" "TIMER_0\0" \
- "f\x34\x04" "TIMER\0" \
- "b\x32" "IPD_DRP\0" \
- "b\x30" "GMX_DRP\0" \
- "b\x2f" "TRACE\0" \
- "b\x2e" "RML\0" \
- "b\x2d" "TWSI\0" \
- "b\x2c" "WDOG_SUM\0" \
- "b\x2b" "PCI_MSI_63_48\0" \
- "b\x2a" "PCI_MSI_47_32\0" \
- "b\x29" "PCI_MSI_31_16\0" \
- "b\x28" "PCI_MSI_15_0\0" \
- "f\x28\x04" "PCI_MSI\0" \
- "b\x27" "PCI_INT_D\0" \
- "b\x26" "PCI_INT_C\0" \
- "b\x25" "PCI_INT_B\0" \
- "f\x24\x04" "PCI_INT\0" \
- "b\x24" "PCI_INT_A\0" \
- "b\x23" "UART_1\0" \
- "b\x22" "UART_0\0" \
- "f\x22\x02" "UART\0" \
- "b\x21" "MBOX_31_16\0" \
- "f\x20\x02" "MBOX\0" \
- "b\x20" "MBOX_15_0\0" \
- "b\x1f" "GPIO_15\0" \
- "b\x1e" "GPIO_14\0" \
- "b\x1d" "GPIO_13\0" \
- "b\x1c" "GPIO_12\0" \
- "b\x1b" "GPIO_11\0" \
- "b\x1a" "GPIO_10\0" \
- "b\x19" "GPIO_9\0" \
- "b\x18" "GPIO_8\0" \
- "b\x17" "GPIO_7\0" \
- "b\x16" "GPIO_6\0" \
- "b\x15" "GPIO_5\0" \
- "b\x14" "GPIO_4\0" \
- "b\x13" "GPIO_3\0" \
- "b\x12" "GPIO_2\0" \
- "b\x11" "GPIO_1\0" \
- "b\x10" "GPIO_0\0" \
- "f\x10\x10" "GPIO\0" \
- "b\x0f" "WORKQ_15\0" \
- "b\x0e" "WORKQ_14\0" \
- "b\x0d" "WORKQ_13\0" \
- "b\x0c" "WORKQ_12\0" \
- "b\x0b" "WORKQ_11\0" \
- "b\x0a" "WORKQ_10\0" \
- "b\x09" "WORKQ_9\0" \
- "b\x08" "WORKQ_8\0" \
- "b\x07" "WORKQ_7\0" \
- "b\x06" "WORKQ_6\0" \
- "b\x05" "WORKQ_5\0" \
- "b\x04" "WORKQ_4\0" \
- "b\x03" "WORKQ_3\0" \
- "b\x02" "WORKQ_2\0" \
- "b\x01" "WORKQ_1\0" \
- "b\x00" "WORKQ_0\0" \
- "f\x00\x10" "WORKQ\0"
#define CIU_INT0_SUM0_BITS CIU_INTX_SUM0_BITS
#define CIU_INT1_SUM0_BITS CIU_INTX_SUM0_BITS
#define CIU_INT2_SUM0_BITS CIU_INTX_SUM0_BITS
#define CIU_INT3_SUM0_BITS CIU_INTX_SUM0_BITS
#define CIU_INT32_SUM0_BITS CIU_INTX_SUM0_BITS
-#define CIU_INT_SUM1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "WDOG\0"
-
-#define CIU_INTX_EN0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3a" "MPI\0" \
- "b\x39" "PCM\0" \
- "b\x38" "USB\0" \
- "b\x37" "TIMER_3\0" \
- "b\x36" "TIMER_2\0" \
- "b\x35" "TIMER_1\0" \
- "b\x34" "TIMER_0\0" \
- "f\x34\x04" "TIMER\0" \
- "b\x32" "IPD_DRP\0" \
- "b\x30" "GMX_DRP\0" \
- "b\x2f" "TRACE\0" \
- "b\x2e" "RML\0" \
- "b\x2d" "TWSI\0" \
- "b\x2c" "WDOG_SUM\0" \
- "b\x2b" "PCI_MSI_63_48\0" \
- "b\x2a" "PCI_MSI_47_32\0" \
- "b\x29" "PCI_MSI_31_16\0" \
- "b\x28" "PCI_MSI_15_0\0" \
- "f\x28\x04" "PCI_MSI\0" \
- "b\x27" "PCI_INT_D\0" \
- "b\x26" "PCI_INT_C\0" \
- "b\x25" "PCI_INT_B\0" \
- "f\x24\x04" "PCI_INT\0" \
- "b\x24" "PCI_INT_A\0" \
- "b\x23" "UART_1\0" \
- "b\x22" "UART_0\0" \
- "f\x22\x02" "UART\0" \
- "b\x21" "MBOX_31_16\0" \
- "f\x20\x02" "MBOX\0" \
- "b\x20" "MBOX_15_0\0" \
- "b\x1f" "GPIO_15\0" \
- "b\x1e" "GPIO_14\0" \
- "b\x1d" "GPIO_13\0" \
- "b\x1c" "GPIO_12\0" \
- "b\x1b" "GPIO_11\0" \
- "b\x1a" "GPIO_10\0" \
- "b\x19" "GPIO_9\0" \
- "b\x18" "GPIO_8\0" \
- "b\x17" "GPIO_7\0" \
- "b\x16" "GPIO_6\0" \
- "b\x15" "GPIO_5\0" \
- "b\x14" "GPIO_4\0" \
- "b\x13" "GPIO_3\0" \
- "b\x12" "GPIO_2\0" \
- "b\x11" "GPIO_1\0" \
- "b\x10" "GPIO_0\0" \
- "f\x10\x10" "GPIO\0" \
- "b\x0f" "WORKQ_15\0" \
- "b\x0e" "WORKQ_14\0" \
- "b\x0d" "WORKQ_13\0" \
- "b\x0c" "WORKQ_12\0" \
- "b\x0b" "WORKQ_11\0" \
- "b\x0a" "WORKQ_10\0" \
- "b\x09" "WORKQ_9\0" \
- "b\x08" "WORKQ_8\0" \
- "b\x07" "WORKQ_7\0" \
- "b\x06" "WORKQ_6\0" \
- "b\x05" "WORKQ_5\0" \
- "b\x04" "WORKQ_4\0" \
- "b\x03" "WORKQ_3\0" \
- "b\x02" "WORKQ_2\0" \
- "b\x01" "WORKQ_1\0" \
- "b\x00" "WORKQ_0\0" \
- "f\x00\x10" "WORKQ\0"
#define CIU_INT0_EN0_BITS CIU_INTX_EN0_BITS
#define CIU_INT1_EN0_BITS CIU_INTX_EN0_BITS
#define CIU_INT2_EN0_BITS CIU_INTX_EN0_BITS
#define CIU_INT3_EN0_BITS CIU_INTX_EN0_BITS
#define CIU_INT32_EN0_BITS CIU_INTX_EN0_BITS
-#define CIU_INTX_EN1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "WDOG\0"
#define CIU_INT0_EN1_BITS CIU_INTX_EN1_BITS
#define CIU_INT1_EN1_BITS CIU_INTX_EN1_BITS
#define CIU_INT2_EN1_BITS CIU_INTX_EN1_BITS
#define CIU_INT3_EN1_BITS CIU_INTX_EN1_BITS
#define CIU_INT32_EN1_BITS CIU_INTX_EN1_BITS
-#define CIU_TIMX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x24" "ONE_SHOT\0" \
- "f\x00\x24" "LEN\0"
#define CIU_TIM0_BITS CIU_TIMX_BITS
#define CIU_TIM1_BITS CIU_TIMX_BITS
#define CIU_TIM2_BITS CIU_TIMX_BITS
#define CIU_TIM3_BITS CIU_TIMX_BITS
#define CIU_TIM32_BITS CIU_TIMX_BITS
-#define CIU_WDOGX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x2d" "GSTOPEN\0" \
- "b\x2c" "DSTOP\0" \
- "f\x14\x18" "CNT\0" \
- "f\x04\x10" "LEN\0" \
- "f\x02\x02" "STATE\0" \
- "f\x00\x02" "MODE\0"
#define CIU_WDOG0_BITS CIU_WDOGX_BITS
#define CIU_WDOG1_BITS CIU_WDOGX_BITS
#if 0
-#define CIU_PP_POKEX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
#define CIU_PP_POKE0_BITS CIU_PP_POKEX_BITS
#define CIU_PP_POKE1_BITS CIU_PP_POKEX_BITS
#endif
-#define CIU_MBOX_SETX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "SET\0"
#define CIU_MBOX_SET0_BITS CIU_MBOX_SETX_BITS
#define CIU_MBOX_SET1_BITS CIU_MBOX_SETX_BITS
-#define CIU_MBOX_CLRX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CLR\0"
#define CIU_MBOX_CLR0_BITS CIU_MBOX_CLRX_BITS
#define CIU_MBOX_CLR1_BITS CIU_MBOX_CLRX_BITS
-#define CIU_PP_RST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "RST0\0"
-
-#define CIU_PP_DBG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "PPDBG\0"
-
-#define CIU_GSTOP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "GSTOP\0"
-
-#define CIU_NMI_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "NMI\0"
-
-#define CIU_DINT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "DINT\0"
-
-#define CIU_FUSE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "FUSE\0"
-
-#define CIU_BIST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x04" "BIST\0"
-
-#define CIU_SOFT_BIST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "SOFT_BIST\0"
-
-#define CIU_SOFT_RST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "SOFT_RST\0"
-
-#define CIU_SOFT_PRST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x02" "HOST64\0" \
- "b\x01" "NPI\0" \
- "b\x00" "SOFT_PRST\0"
-
-#define CIU_PCI_INTA_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x02" "INT\0"
-
#endif /* _OCTEON_CIUREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_corereg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.2 Mon Jun 1 22:55:12 2015
+++ src/sys/arch/mips/cavium/dev/octeon_corereg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_corereg.h,v 1.2 2015/06/01 22:55:12 matt Exp $ */
+/* $NetBSD: octeon_corereg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -473,35 +473,6 @@
#define CP0_CVMCTL_LE UINT64_C(0x0000000000000002)
#define CP0_CVMCTL_USELY UINT64_C(0x0000000000000001)
-#define CP0_CVMCTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1f" "FUSE_STARTBIT\0" \
- "b\x1c" "NODFA_CP21\0" \
- "b\x1b" "NOMUL\0" \
- "b\x1a" "NOCRYPTO\0" \
- "b\x19" "RST_SHT\0" \
- "b\x18" "BIST_DIS\0" \
- "b\x17" "DISSETPRED\0" \
- "b\x16" "DISJRPRED\0" \
- "b\x15" "DISICACHE\0" \
- "b\x14" "DISWAIT\0" \
- "b\x13" "DEFET\0" \
- "b\x12" "DISCO\0" \
- "b\x11" "DISCE\0" \
- "b\x10" "DDCLK\0" \
- "b\x0f" "DCICLK\0" \
- "b\x0e" "REPUN\0" \
- "b\x0d" "IPREF\0" \
- "b\x0c" "USEUN\0" \
- "b\x0b" "DISIOCACHE\0" \
- "b\x0a" "IRAND\0" \
- "f\x07\x03" "IPPCI\0" \
- "f\x04\x03" "IPTI\0" \
- "b\x01" "LE\0" \
- "b\x00" "USELY\0"
-
/* CvmMemCtl Register */
#define CP0_CVMMEMCTL_TLBBIST UINT64_C(0x8000000000000000)
@@ -535,39 +506,6 @@
#define CP0_CVMMEMCTL_CVMSEGENAU UINT64_C(0x0000000000000040)
#define CP0_CVMMEMCTL_LMEMSZ UINT64_C(0x000000000000003f)
-#define CP0_CVMMEMCTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3f" "TLBBIST\0" \
- "b\x3e" "L1CBIST\0" \
- "b\x3d" "L1DBIST\0" \
- "b\x3c" "DCMBIST\0" \
- "b\x3b" "PTGBIST\0" \
- "b\x3a" "WBFBIST\0" \
- "b\x23" "DISMARKWBLONGTO\0" \
- "b\x22" "DISMRGCLRWBTO\0" \
- "f\x20\x02" "IOBDMASCRMSB\0" \
- "b\x1f" "SYNCWSMARKED\0" \
- "b\x1e" "DISSYNCWS\0" \
- "b\x1d" "DISWBFST\0" \
- "b\x1c" "XKMEMENAS\0" \
- "b\x1b" "XKMEMENAU\0" \
- "b\x1a" "XKIOENAS\0" \
- "b\x19" "XKIOENAU\0" \
- "b\x18" "ALLSYNCW\0" \
- "b\x17" "NOMERGE\0" \
- "f\x15\x02" "DIDTTO\0" \
- "b\x14" "CSRCLKALWYS\0" \
- "b\x13" "MCLKALWYS\0" \
- "f\x10\x03" "WBFLTIME\0" \
- "b\x0f" "ISTRNOL2\0" \
- "f\x0b\x04" "WBTHRESH\0" \
- "b\x08" "CVMSEGENAK\0" \
- "b\x07" "CVMSEGENAS\0" \
- "b\x06" "CVMSEGENAU\0" \
- "f\x00\x06" "LMEMSZ\0"
-
/* CvmCount Register */
/* Multi-Core Debug Register */
Index: src/sys/arch/mips/cavium/dev/octeon_fpareg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_fpareg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fpareg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_fpareg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -159,90 +159,6 @@
#define FPA_QUE_ACT_ACT_QUE UINT64_C(0x000000001c000000)
#define FPA_QUE_ACT_ACT_INDX UINT64_C(0x0000000003ffffff)
-/* ---- snprintb(9) */
-
-#define FPA_INT_SUM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1b" "Q7_PERR\0" \
- "b\x1a" "Q7_COFF\0" \
- "b\x19" "Q7_UND\0" \
- "b\x18" "Q6_PERR\0" \
- "b\x17" "Q6_COFF\0" \
- "b\x16" "Q6_UND\0" \
- "b\x15" "Q5_PERR\0" \
- "b\x14" "Q5_COFF\0" \
- "b\x13" "Q5_UND\0" \
- "b\x12" "Q4_PERR\0" \
- "b\x11" "Q4_COFF\0" \
- "b\x10" "Q4_UND\0" \
- "b\x0f" "Q3_PERR\0" \
- "b\x0e" "Q3_COFF\0" \
- "b\x0d" "Q3_UND\0" \
- "b\x0c" "Q2_PERR\0" \
- "b\x0b" "Q2_COFF\0" \
- "b\x0a" "Q2_UND\0" \
- "b\x09" "Q1_PERR\0" \
- "b\x08" "Q1_COFF\0" \
- "b\x07" "Q1_UND\0" \
- "b\x06" "Q0_PERR\0" \
- "b\x05" "Q0_COFF\0" \
- "b\x04" "Q0_UND\0" \
- "b\x03" "FED1_DBE\0" \
- "b\x02" "FED1_SBE\0" \
- "b\x01" "FED0_DBE\0" \
- "b\x00" "FED0_SBE\0"
-
-#define FPA_INT_ENB_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1b" "Q7_PERR\0" \
- "b\x1a" "Q7_COFF\0" \
- "b\x19" "Q7_UND\0" \
- "b\x18" "Q6_PERR\0" \
- "b\x17" "Q6_COFF\0" \
- "b\x16" "Q6_UND\0" \
- "b\x15" "Q5_PERR\0" \
- "b\x14" "Q5_COFF\0" \
- "b\x13" "Q5_UND\0" \
- "b\x12" "Q4_PERR\0" \
- "b\x11" "Q4_COFF\0" \
- "b\x10" "Q4_UND\0" \
- "b\x0f" "Q3_PERR\0" \
- "b\x0e" "Q3_COFF\0" \
- "b\x0d" "Q3_UND\0" \
- "b\x0c" "Q2_PERR\0" \
- "b\x0b" "Q2_COFF\0" \
- "b\x0a" "Q2_UND\0" \
- "b\x09" "Q1_PERR\0" \
- "b\x08" "Q1_COFF\0" \
- "b\x07" "Q1_UND\0" \
- "b\x06" "Q0_PERR\0" \
- "b\x05" "Q0_COFF\0" \
- "b\x04" "Q0_UND\0" \
- "b\x03" "FED1_DBE\0" \
- "b\x02" "FED1_SBE\0" \
- "b\x01" "FED0_DBE\0" \
- "b\x00" "FED0_SBE\0"
-
-#define FPA_CTL_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x11" "RESET\0" \
- "b\x10" "USE_LDT\0" \
- "b\x0f" "USE_STT\0" \
- "b\x0e" "ENB\0" \
- "f\x07\x07" "MEM1_ERR\0" \
- "f\x00\x07" "MEM0_ERR\0"
-
-#define FPA_QUEX_AVAILABLE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x1d" "QUE_SIZ\0"
#define FPA_QUE0_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
#define FPA_QUE1_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
#define FPA_QUE2_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
@@ -252,33 +168,6 @@
#define FPA_QUE6_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
#define FPA_QUE7_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_WART_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "CTL\0"
-
-#define FPA_WART_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "STATUS\0"
-
-#define FPA_BIST_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x04" "FRD\0" \
- "b\x03" "FPF0\0" \
- "b\x02" "FPF1\0" \
- "b\x01" "FFR\0" \
- "b\x00" "FDR\0"
-
-#define FPA_QUEX_PAGE_INDEX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x19" "PG_NUM\0"
#define FPA_QUE0_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
#define FPA_QUE1_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
#define FPA_QUE2_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
@@ -288,20 +177,6 @@
#define FPA_QUE6_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
#define FPA_QUE7_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE_EXP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1a\x03" "EXP_QUE\0" \
- "f\x00\x1a" "EXP_INDX\0"
-
-#define FPA_QUE_ACT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1a\x03" "ACT_QUE\0" \
- "f\x00\x1a" "ACT_INDX\0"
-
/* ---- operations */
/*
Index: src/sys/arch/mips/cavium/dev/octeon_gmxreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_gmxreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmxreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_gmxreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -626,453 +626,6 @@
#define GMX0_BASE_IF0 0x0001180008000000ULL
#define GMX0_BASE_IF_SIZE (GMX0_BASE_PORT_SIZE * GMX_PORT_NUNITS)
-/* for snprintb(9) */
-
-#define RXN_INT_REG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x12" "PHY_DUPX\0" \
- "b\x11" "PHY_SPD\0" \
- "b\x10" "PHY_LINK\0" \
- "b\x0f" "IFGERR\0" \
- "b\x0e" "COLDET\0" \
- "b\x0d" "FALERR\0" \
- "b\x0c" "RSVERR\0" \
- "b\x0b" "PCTERR\0" \
- "b\x0a" "OVRERR\0" \
- "b\x09" "NIBERR\0" \
- "b\x08" "SKPERR\0" \
- "b\x07" "RCVERR\0" \
- "b\x06" "LENERR\0" \
- "b\x05" "ALNERR\0" \
- "b\x04" "FCSERR\0" \
- "b\x03" "JABBER\0" \
- "b\x02" "MAXERR\0" \
- "b\x01" "CAREXT\0" \
- "b\x00" "MINERR\0"
-#define RXN_INT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x12" "PHY_DUPX\0" \
- "b\x11" "PHY_SPD\0" \
- "b\x10" "PHY_LINK\0" \
- "b\x0f" "IFGERR\0" \
- "b\x0e" "COLDET\0" \
- "b\x0d" "FALERR\0" \
- "b\x0c" "RSVERR\0" \
- "b\x0b" "PCTERR\0" \
- "b\x0a" "OVRERR\0" \
- "b\x09" "NIBERR\0" \
- "b\x08" "SKPERR\0" \
- "b\x07" "RCVERR\0" \
- "b\x06" "LENERR\0" \
- "b\x05" "ALNERR\0" \
- "b\x04" "FCSERR\0" \
- "b\x03" "JABBER\0" \
- "b\x02" "MAXERR\0" \
- "b\x01" "CAREXT\0" \
- "b\x00" "MINERR\0"
-#define PRTN_CFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x03" "SLOTTIME\0" \
- "b\x02" "DUPLEX\0" \
- "b\x01" "SPEED\0" \
- "b\x00" "EN\0"
-#define RXN_FRM_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0a" "NULL_DIS\0" \
- "b\x09" "PRE_ALIGN\0" \
- "b\x08" "PAD_LEN\0" \
- "b\x07" "VLAN_LEN\0" \
- "b\x06" "PRE_FREE\0" \
- "b\x05" "CTL_SMAC\0" \
- "b\x04" "CTL_MCST\0" \
- "b\x03" "CTL_BCK\0" \
- "b\x02" "CTL_DRP\0" \
- "b\x01" "PRE_STRP\0" \
- "b\x00" "PRE_CHK\0"
-#define RXN_FRM_CHK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x09" "NIBERR\0" \
- "b\x08" "SKPERR\0" \
- "b\x07" "RCVERR\0" \
- "b\x06" "LENERR\0" \
- "b\x05" "ALNERR\0" \
- "b\x04" "FCSERR\0" \
- "b\x03" "JABBER\0" \
- "b\x02" "MAXERR\0" \
- "b\x01" "CAREXT\0" \
- "b\x00" "MINERR\0"
-/* RXN_FRM_MIN */
-/* RXN_FRM_MAX */
-#define RXN_JABBER_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "CNT\0"
-#define RXN_DECISION_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x05" "CNT\0"
-#define RXN_UDD_SKP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x08" "FCSSEL\0" \
- "f\x00\x07" "LEN\0"
-#define RXN_STATS_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "RD_CLR\0"
-#define RXN_IFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x04" "IFG\0"
-#define RXN_RX_INBND_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x03" "DUPLEX\0" \
- "f\x01\x02" "SPEED\0" \
- "b\x00" "STATUS\0"
-#define RXN_STATS_PKTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CNT\0"
-#define RXN_STATS_OCTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "CNT\0"
-#define RXN_STATS_PKTS_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CNT\0"
-#define RXN_STATS_OCTS_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "CNT\0"
-#define RXN_STATS_PKTS_DMAC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CNT\0"
-#define RXN_STATS_OCTS_DMAC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "CNT\0"
-#define RXN_STATS_PKTS_DRP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CNT\0"
-#define RXN_STATS_OCTS_DRP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "CNT\0"
-#define RXN_STATS_PKTS_BAD_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "CNT\0"
-#define RXN_ADR_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x03" "CAM_MODE\0" \
- "f\x01\x02" "MCST\0" \
- "b\x00" "BCST\0"
-#define RXN_ADR_CAM_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x08" "EN\0"
-/* RXN_ADR_CAM0 */
-/* RXN_ADR_CAM1 */
-/* RXN_ADR_CAM2 */
-/* RXN_ADR_CAM3 */
-/* RXN_ADR_CAM4 */
-/* RXN_ADR_CAM5 */
-#define TXN_CLK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x06" "CLK_CNT\0"
-#define TXN_THRESH_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x06" "CNT\0"
-#define TXN_APPEND_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x03" "FORCE_FCS\0" \
- "b\x02" "FCS\0" \
- "b\x01" "PAD\0" \
- "b\x00" "PREAMBLE\0"
-#define TXN_SLOT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x0a" "SLOT\0"
-#define TXN_BURST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "BURST\0"
-/* SMAC0 */
-#define TXN_PAUSE_PKT_TIME_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "TIME\0"
-#define TXN_MIN_PKT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x08" "MIN_SIZE\0"
-#define TXN_PAUSE_PKT_INTERVAL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "INTERVAL\0"
-#define TXN_SOFT_PAUSE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "TIME\0"
-#define TXN_PAUSE_TOGO_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "TIME\0"
-#define TXN_PAUSE_ZERO_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "SEND\0"
-#define TXN_STATS_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "RD_CLR\0"
-#define TXN_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x01" "XSDEF_EN\0" \
- "b\x00" "XSCOL_EN\0"
-#define TXN_STAT0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "XSDEF\0" \
- "f\x00\x20" "XSCOL\0"
-#define TXN_STAT1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "SCOL\0" \
- "f\x00\x20" "MSCOL\0"
-#define TXN_STAT2_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "OCTS\0"
-#define TXN_STAT3_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "PKTS\0"
-#define TXN_STAT4_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "HIST1\0" \
- "f\x00\x20" "HIST0\0"
-#define TXN_STAT5_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "HIST3\0" \
- "f\x00\x20" "HIST2\0"
-#define TXN_STAT6_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "HIST5\0" \
- "f\x00\x20" "HIST4\0"
-#define TXN_STAT7_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "HIST7\0" \
- "f\x00\x20" "HIST6\0"
-#define TXN_STAT8_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "MCST\0" \
- "f\x00\x20" "BCST\0"
-#define TXN_STAT9_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "UNDFLW\0" \
- "f\x00\x20" "CTL\0"
-/* BIST0 */
-#define RX_PRTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x03" "PRTS\0"
-#define RX_BP_DROPN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x06" "MARK\0"
-#define RX_BP_ONN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x09" "MARK\0"
-#define RX_BP_OFFN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x06" "MARK\0"
-#define TX_PRTS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x05" "PRTS\0"
-#define TX_IFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x04\x04" "IFG2\0" \
- "f\x00\x04" "IFG1\0"
-#define TX_JAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x08" "JAM\0"
-#define TX_COL_ATTEMPT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x05" "LIMIT\0"
-#define TX_PAUSE_PKT_DMAC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x30" "DMAC\0"
-#define TX_PAUSE_PKT_TYPE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "TYPE\0"
-#define TX_OVR_BP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x08\x03" "EN\0" \
- "f\x04\x03" "BP\0" \
- "f\x00\x03" "IGN_FULL\0"
-#define TX_BP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x03" "SR_BP\0"
-#define TX_CORRUPT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x03" "CORRUPT\0"
-#define RX_PRT_INFO_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x03" "DROP\0" \
- "f\x00\x03" "COMMIT\0"
-#define TX_LFSR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "LFSR\0"
-#define TX_INT_REG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x03" "LATE_COL\0" \
- "f\x0c\x03" "XSDEF\0" \
- "f\x08\x03" "XSCOL\0" \
- "f\x02\x03" "UNDFLW\0" \
- "b\x00" "PKO_NXA\0"
-#define TX_INT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x03" "LATE_COL\0" \
- "f\x0c\x03" "XSDEF\0" \
- "f\x08\x03" "XSCOL\0" \
- "f\x02\x03" "UNDFLW\0" \
- "b\x00" "PKO_NXA\0"
-#define NXA_ADR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x06" "PRT\0"
-#define BAD_REG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1b\x04" "INB_NXA\0" \
- "b\x1a" "STATOVR\0" \
- "f\x16\x03" "LOSTSTAT\0" \
- "f\x02\x03" "OUT_OVR\0"
-#define STAT_BP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x10" "BP\0" \
- "f\x00\x10" "CNT\0"
-#define TX_CLK_MSKN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x00" "MSK\0"
-#define RX_TX_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x04\x03" "TX\0" \
- "f\x00\x03" "RX\0"
-#define INF_MODE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x02" "P0MII\0" \
- "b\x01" "EN\0" \
- "b\x00" "TYPE\0"
-
#define GMX0_RX0_INT_REG_BITS RXN_INT_REG_BITS
#define GMX0_RX0_INT_EN_BITS RXN_INT_EN_BITS
#define GMX0_PRT0_CFG_BITS PRTN_CFG_BITS
Index: src/sys/arch/mips/cavium/dev/octeon_ipdreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipdreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipdreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_ipdreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -427,305 +427,4 @@
#define IPD_WQE_L4_SYN_RST 12
#define IPD_WQE_L4_SYN_FIN 13
-#define IPD_1ST_MBUFF_SKIP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x06\x3a" "63_6\0" \
- "f\x00\x06" "SZ\0"
-#define IPD_NOT_1ST_MBUFF_SKIP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x06\x3a" "63_6\0" \
- "f\x00\x06" "SZ\0"
-#define IPD_PACKET_MBUFF_SIZE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x0c\x34" "63_12\0" \
- "f\x00\x0c" "MB_SIZE\0"
-#define IPD_CTL_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x0a\x36" "63_10\0" \
- "b\x09" "LEN_M8\0" \
- "b\x08" "RESET\0" \
- "b\x07" "ADDPKT\0" \
- "b\x06" "NADDBUF\0" \
- "b\x05" "PKT_LEND\0" \
- "b\x04" "WQE_LEND\0" \
- "b\x03" "PBP_EN\0" \
- "f\x01\x02" "OPC_MODE\0" \
- "b\x00" "IPD_EN\0"
-#define IPD_WQE_FPA_QUEUE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x3d" "63_3\0" \
- "f\x00\x03" "WQE_QUE\0"
-#define IPD_PORT0_BP_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT1_BP_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT2_BP_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT32_BP_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_SUB_PORT_BP_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1f\x21" "63_18\0" \
- "f\x19\x06" "PORT\0" \
- "f\x00\x19" "PAGE_CNT\0"
-#define IPD_1ST_NEXT_PTR_BACK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x04\x3c" "63_4\0" \
- "f\x00\x04" "BACK\0"
-#define IPD_2ND_NEXT_PTR_BACK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x04\x3c" "63_4\0" \
- "f\x00\x04" "BACK\0"
-#define IPD_INT_ENB_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x05\x3b" "63_4\0" \
- "b\x04" "BP_SUB\0" \
- "b\x03" "PRC_PAR3\0" \
- "b\x02" "PRC_PAR2\0" \
- "b\x01" "PRC_PAR1\0" \
- "b\x00" "PRC_PAR0\0"
-#define IPD_INT_SUM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x05\x3b" "63_4\0" \
- "b\x04" "BP_SUB\0" \
- "b\x03" "PRC_PAR3\0" \
- "b\x02" "PRC_PAR2\0" \
- "b\x01" "PRC_PAR1\0" \
- "b\x00" "PRC_PAR0\0"
-#define IPD_SUB_PORT_FCS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x3d" "63_3\0" \
- "f\x00\x03" "PORT_BIT\0"
-#define IPD_QOS0_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS1_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS2_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS3_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS4_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS5_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS6_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_QOS7_RED_MARKS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT_BP_COUNTERS_PAIR0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT_BP_COUNTERS_PAIR1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT_BP_COUNTERS_PAIR2_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PORT_BP_COUNTERS_PAIR32_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_PORT_ENABLE_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x32\x0e" "PRB_DLY\0" \
- "f\x24\x0e" "AVG_DLY\0" \
- "f\x00\x24" "PRT_ENB\0"
-#define IPD_RED_QUE0_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE1_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE2_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE3_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE4_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE5_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE6_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_RED_QUE7_PARAM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define IPD_PTR_COUNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x13\x2d" "63_19\0" \
- "b\x12" "PKTV_CNT\0" \
- "b\x11" "WQEV_CNT\0" \
- "f\x0e\x03" "PFIF_CNT\0" \
- "f\x07\x07" "PKT_PCNT\0" \
- "f\x00\x07" "WQE_PCNT\0"
-#define IPD_BP_PRT_RED_END_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x24\x1c" "63_36\0" \
- "f\x00\x24" "PRT_ENB\0"
-#define IPD_QUE0_FREE_PAGE_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "63_32\0" \
- "f\x00\x20" "Q0_PCNT\0"
-#define IPD_CLK_COUNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x40" "CLK_CNT\0"
-#define IPD_PWP_PTR_FIFO_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x3d\x03" "63_61\0" \
- "f\x36\x07" "MAX_CNTS\0" \
- "f\x2e\x08" "WRADDR\0" \
- "f\x26\x08" "PRADDR\0" \
- "f\x09\x1d" "PTR\0" \
- "b\x08" "CENA\0" \
- "f\x00\x08" "RADDR\0"
-#define IPD_PRC_HOLD_PTR_FIFO_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x27\x19" "63_39\0" \
- "f\x24\x03" "MAX_PTR\0" \
- "f\x21\x03" "PRADDR\0" \
- "f\x04\x1d" "PTR\0" \
- "b\x03" "CENA\0" \
- "f\x00\x03" "RADDR\0"
-#define IPD_PRC_PORT_PTR_FIFO_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x2c\x14" "63_44\0" \
- "f\x25\x07" "MAX_PTR\0" \
- "f\x08\x1d" "PTR\0" \
- "b\x07" "CENA\0" \
- "f\x00\x07" "RADDR\0"
-#define IPD_PKT_PTR_VALID_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1d\x23" "63_29\0" \
- "f\x00\x1d" "PTR\0"
-#define IPD_WQE_PTR_VALID_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x1d\x23" "63_29\0" \
- "f\x00\x1d" "PTR\0"
-#define IPD_BIST_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x30" "63_29\0" \
- "b\x0f" "PWQ_WQED\0" \
- "b\x0e" "PWQ_WP1\0" \
- "b\x0d" "PWQ_POW\0" \
- "b\x0c" "IPQ_PBE1\0" \
- "b\x0b" "IPQ_PBE0\0" \
- "b\x0a" "PBM3\0" \
- "b\x09" "PBM2\0" \
- "b\x08" "PBM1\0" \
- "b\x07" "PBM0\0" \
- "b\x06" "PBM_WORD\0" \
- "b\x05" "PWQ1\0" \
- "b\x04" "PWQ0\0" \
- "b\x03" "PRC_OFF\0" \
- "b\x02" "IPD_OLD\0" \
- "b\x01" "IPD_NEW\0" \
- "b\x00" "PWP\0"
-
#endif /* _OCTEON_IPDREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_mpireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_mpireg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_mpireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_mpireg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -76,40 +76,6 @@
#define MPI_DATX_XXX_63_8 UINT64_C(0xffffffffffffff00)
#define MPI_DATX_DATA UINT64_C(0x00000000000000ff)
-/* ---- snprintb */
-
-#define MPI_CFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x0d" "CLKDIV\0" \
- "b\x0b" "CSLATE\0" \
- "b\x0a" "TRITX\0" \
- "f\x08\x02" "IDLECLKS\0" \
- "b\x07" "CSHI\0" \
- "b\x06" "CSENA\0" \
- "b\x05" "INT_ENA\0" \
- "b\x04" "LSBFIRST\0" \
- "b\x03" "WIREOR\0" \
- "b\x02" "CLK_CONT\0" \
- "b\x01" "IDLELO\0" \
- "b\x00" "ENABLE\0"
-
-#define MPI_STS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x08\x05" "RXNUM\0" \
- "b\x00" "BUSY\0"
-
-#define MPI_TX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x10" "LEAVECS\0" \
- "f\x08\x05" "TXNUM\0" \
- "f\x00\x05" "TOTNUM\0"
-
/* ---- bus_space */
#define MPI_BASE 0x0001070000001000ULL
Index: src/sys/arch/mips/cavium/dev/octeon_pipreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pipreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_pipreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -139,6 +139,7 @@
#define PIP_PRT_TAG32_OFFSET 0x500ULL
#define PIP_QOS_DIFF0_OFFSET 0x600ULL
/* PIP_QOS_DIFF[1-63] */
+#define PIP_STAT0_PRT_OFFSET(i) (0x800ULL + (i) * 0x50)
#define PIP_STAT0_PRT0_OFFSET 0x800ULL
#define PIP_STAT0_PRT1_OFFSET 0x850ULL
#define PIP_STAT0_PRT2_OFFSET 0x8a0ULL
@@ -622,122 +623,10 @@
#define PIP_GMX_FCS_ERR PIP_WQE_WORD2_RE_OPCODE_GMXFCS
#define PIP_ALIGN_ERR PIP_WQE_WORD2_RE_OPCODE_ALIGN
-#define PIP_BIST_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x12\x2e" "63_13\0" \
- "f\x00\x12" "BIST\0"
-#define PIP_INT_REG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x09\x37" "63_9\0" \
- "b\x08" "BEPERR\0" \
- "b\x07" "FEPERR\0" \
- "b\x06" "6\0" \
- "b\x05" "SKPRUNT\0" \
- "b\x04" "BADTAG\0" \
- "b\x03" "PRTNXA\0" \
- "f\x01\x02" "2_1\0" \
- "b\x00" "PKTDRP\0"
-#define PIP_INT_EN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x09\x37" "63_9\0" \
- "b\x08" "BEPERR\0" \
- "b\x07" "FEPERR\0" \
- "b\x06" "6\0" \
- "b\x05" "SKPRUNT\0" \
- "b\x04" "BADTAG\0" \
- "b\x03" "PRTNXA\0" \
- "f\x01\x02" "2_1\0" \
- "b\x00" "PKTDRP\0"
-#define PIP_STAT_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x01\x3f" "63_1\0" \
- "b\x00" "RDCLR\0"
-#define PIP_GBL_CTL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x11\x2f" "63_17\0" \
- "b\x10" "IGNRS\0" \
- "b\x0f" "VS_WQE\0" \
- "b\x0e" "VS_QOS\0" \
- "b\x0d" "L2MAL\0" \
- "b\x0c" "TCP_FLAG\0" \
- "b\x0b" "L4_LEN\0" \
- "b\x0a" "L4_CHK\0" \
- "b\x09" "L4_PRT\0" \
- "b\x08" "L4_MAL\0" \
- "f\x06\x02" "7_6\0" \
- "f\x04\x02" "IP6_EEXT\0" \
- "b\x03" "IP4_OPTS\0" \
- "b\x02" "IP_HOP\0" \
- "b\x01" "IP_MAL\0" \
- "b\x00" "IP_CHK\0"
-#define PIP_GBL_CFG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x13\x2d" "63_19\0" \
- "b\x12" "TAG_SYN\0" \
- "b\x11" "IP6_UDP\0" \
- "b\x10" "MAX_L2\0" \
- "f\x0b\x05" "15_11\0" \
- "f\x08\x03" "RAW_SHF\0" \
- "f\x03\x05" "7_3\0" \
- "f\x00\x03" "NIP_SHF\0"
-#define PIP_SOFT_RST_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define PIP_IP_OFFSET_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x03\x3d" "63_3\0" \
- "f\x00\x03" "MASK_OFFSET\0"
-#define PIP_TAG_SECRET_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "63_3\0" \
- "f\x10\x10" "DST\0" \
- "f\x00\x10" "SRC\0"
-#define PIP_TAG_MASK_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x30" "63_16\0" \
- "f\x00\x10" "MASK\0"
-#define PIP_DEC_IPSECN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x12\x2e" "63_18\0" \
- "b\x11" "TCP\0" \
- "b\x10" "UDP\0" \
- "f\x00\x10" "DPRT\0"
#define PIP_DEC_IPSEC0_BITS PIP_DEC_IPSECN_BITS
#define PIP_DEC_IPSEC1_BITS PIP_DEC_IPSECN_BITS
#define PIP_DEC_IPSEC2_BITS PIP_DEC_IPSECN_BITS
#define PIP_DEC_IPSEC3_BITS PIP_DEC_IPSECN_BITS
-#define PIP_RAW_WORD_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x38\x08" "63_56\0" \
- "f\x00\x38" "WORD\0"
-#define PIP_QOS_VLANN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
#define PIP_QOS_VLAN0_BITS PIP_QOS_VLANN_BITS
#define PIP_QOS_VLAN1_BITS PIP_QOS_VLANN_BITS
@@ -747,219 +636,84 @@
#define PIP_QOS_VLAN5_BITS PIP_QOS_VLANN_BITS
#define PIP_QOS_VLAN6_BITS PIP_QOS_VLANN_BITS
#define PIP_QOS_VLAN7_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_WATCHN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x30\x10" "63_48\0" \
- "f\x20\x10" "MASK\0" \
- "f\x1c\x04" "31_28\0" \
- "f\x18\x04" "GRP\0" \
- "b\x17" "23\0" \
- "f\x14\x03" "WATCHER\0" \
- "f\x12\x02" "19_18\0" \
- "f\x10\x02" "TYPE\0" \
- "f\x00\x10" "15_0\0"
+
#define PIP_QOS_WATCH0_BITS PIP_QOS_WATCHN_BITS
#define PIP_QOS_WATCH1_BITS PIP_QOS_WATCHN_BITS
#define PIP_QOS_WATCH2_BITS PIP_QOS_WATCHN_BITS
#define PIP_QOS_WATCH3_BITS PIP_QOS_WATCHN_BITS
-#define PIP_PRT_CFGN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x35\x0b" "63_53\0" \
- "b\x34" "PAD_LEN\0" \
- "b\x33" "VLAN_LEN\0" \
- "b\x32" "LENERR_EN\0" \
- "b\x31" "MAXERR_EN\0" \
- "b\x30" "MINERR_EN\0" \
- "f\x2c\x04" "GRP_WAT_47\0" \
- "f\x28\x04" "QOS_WAT_47\0" \
- "f\x25\x03" "39_37\0" \
- "b\x24" "RAWDRP\0" \
- "f\x22\x02" "TAG_INC\0" \
- "b\x21" "DYN_RS\0" \
- "b\x20" "INST_HDR\0" \
- "f\x1c\x04" "GRP_WAT\0" \
- "b\x1b" "27\0" \
- "f\x18\x03" "QOS\0" \
- "f\x14\x04" "QOS_WAT\0" \
- "b\x13" "19\0" \
- "b\x12" "SPARE\0" \
- "b\x11" "QOS_DIFF\0" \
- "b\x10" "QOS_VLAN\0" \
- "f\x0d\x03" "15_13\0" \
- "b\x0c" "CRC_EN\0" \
- "f\x0a\x02" "11_10\0" \
- "f\x08\x02" "MODE\0" \
- "b\x07" "7\0" \
- "f\x00\x07" "SKIP\0"
+
#define PIP_PRT_CFG0_BITS PIP_PRT_CFGN_BITS
#define PIP_PRT_CFG1_BITS PIP_PRT_CFGN_BITS
#define PIP_PRT_CFG2_BITS PIP_PRT_CFGN_BITS
#define PIP_PRT_CFG32_BITS PIP_PRT_CFGN_BITS
-#define PIP_PRT_TAGN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x28\x18" "63_40\0" \
- "f\x24\x04" "GRPTAGBASE\0" \
- "f\x20\x04" "GRPTAGMASK\0" \
- "b\x1f" "GRPTAG\0" \
- "b\x1e" "SPARE\0" \
- "f\x1c\x02" "TAG_MODE\0" \
- "f\x1a\x02" "INC_VS\0" \
- "b\x19" "INC_VLAN\0" \
- "b\x18" "INC_PRT\0" \
- "b\x17" "IP6_DPRT\0" \
- "b\x16" "IP4_DPRT\0" \
- "b\x15" "IP6_SPRT\0" \
- "b\x14" "IP4_SPRT\0" \
- "b\x13" "IP6_NXTH\0" \
- "b\x12" "IP4_PCTL\0" \
- "b\x11" "IP6_DST\0" \
- "b\x10" "IP4_SRC\0" \
- "b\x0f" "IP6_SRC\0" \
- "b\x0e" "IP4_DST\0" \
- "f\x0c\x02" "TCP6_TAG\0" \
- "f\x0a\x02" "TCP4_TAG\0" \
- "f\x08\x02" "IP6_TAG\0" \
- "f\x06\x02" "IP4_TAG\0" \
- "f\x04\x02" "NON_TAG\0" \
- "f\x00\x04" "GRP\0"
+
#define PIP_PRT_TAG0_BITS PIP_PRT_TAGN_BITS
#define PIP_PRT_TAG1_BITS PIP_PRT_TAGN_BITS
#define PIP_PRT_TAG2_BITS PIP_PRT_TAGN_BITS
#define PIP_PRT_TAG32_BITS PIP_PRT_TAGN_BITS
/* PIP_QOS_DIFF[0-63] */
-#define PIP_STAT0_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "DRP_PKTS\0" \
- "f\x00\x20" "DRP_OCTS\0"
+
#define PIP_STAT0_PRT0_BITS PIP_STAT0_PRTN_BITS
#define PIP_STAT0_PRT1_BITS PIP_STAT0_PRTN_BITS
#define PIP_STAT0_PRT2_BITS PIP_STAT0_PRTN_BITS
#define PIP_STAT0_PRT32_BITS PIP_STAT0_PRTN_BITS
-#define PIP_STAT1_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x30\x10" "63_48\0" \
- "f\x00\x30" "OCTS\0"
+
#define PIP_STAT1_PRT0_BITS PIP_STAT1_PRTN_BITS
#define PIP_STAT1_PRT1_BITS PIP_STAT1_PRTN_BITS
#define PIP_STAT1_PRT2_BITS PIP_STAT1_PRTN_BITS
#define PIP_STAT1_PRT32_BITS PIP_STAT1_PRTN_BITS
-#define PIP_STAT2_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "PKTS\0" \
- "f\x00\x20" "RAW\0"
+
#define PIP_STAT2_PRT0_BITS PIP_STAT2_PRTN_BITS
#define PIP_STAT2_PRT1_BITS PIP_STAT2_PRTN_BITS
#define PIP_STAT2_PRT2_BITS PIP_STAT2_PRTN_BITS
#define PIP_STAT2_PRT32_BITS PIP_STAT2_PRTN_BITS
-#define PIP_STAT3_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "BCST\0" \
- "f\x00\x20" "MCST\0"
+
#define PIP_STAT3_PRT0_BITS PIP_STAT3_PRTN_BITS
#define PIP_STAT3_PRT1_BITS PIP_STAT3_PRTN_BITS
#define PIP_STAT3_PRT2_BITS PIP_STAT3_PRTN_BITS
#define PIP_STAT3_PRT32_BITS PIP_STAT3_PRTN_BITS
-#define PIP_STAT4_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "H65TO127\0" \
- "f\x00\x20" "H64\0"
+
#define PIP_STAT4_PRT0_BITS PIP_STAT4_PRTN_BITS
#define PIP_STAT4_PRT1_BITS PIP_STAT4_PRTN_BITS
#define PIP_STAT4_PRT2_BITS PIP_STAT4_PRTN_BITS
#define PIP_STAT4_PRT32_BITS PIP_STAT4_PRTN_BITS
-#define PIP_STAT5_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "H256TO511\0" \
- "f\x00\x20" "H128TO255\0"
+
#define PIP_STAT5_PRT0_BITS PIP_STAT5_PRTN_BITS
#define PIP_STAT5_PRT1_BITS PIP_STAT5_PRTN_BITS
#define PIP_STAT5_PRT2_BITS PIP_STAT5_PRTN_BITS
#define PIP_STAT5_PRT32_BITS PIP_STAT5_PRTN_BITS
-#define PIP_STAT6_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "H1024TO1518\0" \
- "f\x00\x20" "H512TO1023\0"
+
#define PIP_STAT6_PRT0_BITS PIP_STAT6_PRTN_BITS
#define PIP_STAT6_PRT1_BITS PIP_STAT6_PRTN_BITS
#define PIP_STAT6_PRT2_BITS PIP_STAT6_PRTN_BITS
#define PIP_STAT6_PRT32_BITS PIP_STAT6_PRTN_BITS
-#define PIP_STAT7_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "FCS\0" \
- "f\x00\x20" "H1519\0"
+
#define PIP_STAT7_PRT0_BITS PIP_STAT7_PRTN_BITS
#define PIP_STAT7_PRT1_BITS PIP_STAT7_PRTN_BITS
#define PIP_STAT7_PRT2_BITS PIP_STAT7_PRTN_BITS
#define PIP_STAT7_PRT32_BITS PIP_STAT7_PRTN_BITS
-#define PIP_STAT8_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "FRAG\0" \
- "f\x00\x20" "UNDERSZ\0"
+
#define PIP_STAT8_PRT0_BITS PIP_STAT8_PRTN_BITS
#define PIP_STAT8_PRT1_BITS PIP_STAT8_PRTN_BITS
#define PIP_STAT8_PRT2_BITS PIP_STAT8_PRTN_BITS
#define PIP_STAT8_PRT32_BITS PIP_STAT8_PRTN_BITS
-#define PIP_STAT9_PRTN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "JABBER\0" \
- "f\x00\x20" "OVERSZ\0"
+
#define PIP_STAT9_PRT0_BITS PIP_STAT9_PRTN_BITS
#define PIP_STAT9_PRT1_BITS PIP_STAT9_PRTN_BITS
#define PIP_STAT9_PRT2_BITS PIP_STAT9_PRTN_BITS
#define PIP_STAT9_PRT32_BITS PIP_STAT9_PRTN_BITS
/* PIP_TAG_INC[0-63] */
-#define PIP_STAT_INB_PKTSN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x20" "PIP_STAT_INB_PKTSN\0" \
- "f\x00\x20" "PKTS\0"
+
#define PIP_STAT_INB_PKTS0_BITS PIP_STAT_INB_PKTSN_BITS
#define PIP_STAT_INB_PKTS1_BITS PIP_STAT_INB_PKTSN_BITS
#define PIP_STAT_INB_PKTS2_BITS PIP_STAT_INB_PKTSN_BITS
#define PIP_STAT_INB_PKTS32_BITS PIP_STAT_INB_PKTSN_BITS
-#define PIP_STAT_INB_OCTSN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x30\x10" "PIP_STAT_INB_OCTSN\0" \
- "f\x00\x30" "OCTS\0"
+
#define PIP_STAT_INB_OCTS0_BITS PIP_STAT_INB_OCTSN_BITS
#define PIP_STAT_INB_OCTS1_BITS PIP_STAT_INB_OCTSN_BITS
#define PIP_STAT_INB_OCTS2_BITS PIP_STAT_INB_OCTSN_BITS
#define PIP_STAT_INB_OCTS32_BITS PIP_STAT_INB_OCTSN_BITS
-#define PIP_STAT_INB_ERRSN_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x30" "PIP_STAT_INB_ERRSN\0" \
- "f\x00\x10" "OCTS\0"
+
#define PIP_STAT_INB_ERRS0_BITS PIP_STAT_INB_ERRSN_BITS
#define PIP_STAT_INB_ERRS1_BITS PIP_STAT_INB_ERRSN_BITS
#define PIP_STAT_INB_ERRS2_BITS PIP_STAT_INB_ERRSN_BITS
Index: src/sys/arch/mips/cavium/dev/octeon_powreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_powreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_powreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_powreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -372,24 +372,6 @@
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_XXX_35_34 UINT64_C(0x0000000c00000000)
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TYPE UINT64_C(0x0000000300000000)
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TAG UINT64_C(0x00000000ffffffff)
-#define POW_STATUS_LOAD_RESULT_PEND_TAG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3d" "PEND_SWITCH\0" \
- "b\x3c" "PEND_SWITCH_FULL\0" \
- "b\x3b" "PEND_SWITCH_NULL\0" \
- "b\x3a" "PEND_DESCHED\0" \
- "b\x39" "PEND_DESCHED_SWITCH\0" \
- "b\x38" "PEND_NOSCHED\0" \
- "b\x37" "PEND_NEW_WORK\0" \
- "b\x36" "PEND_NEW_WORK_WAIT\0" \
- "b\x35" "PEND_NULL_RD\0" \
- "b\x34" "PEND_NOSCHED_CLR\0" \
- "f\x28\x0b" "PEND_INDEX\0" \
- "f\x24\x04" "PEND_GRP\0" \
- "f\x20\x02" "PEND_TYPE\0" \
- "f\x00\x20" "PEND_TAG\0"
/* get_cur = 0 and get_wqp = 1 ("pend_wqp") */
#define POW_STATUS_LOAD_RESULT_PEND_WQP_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -406,22 +388,6 @@
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_XXX_51 UINT64_C(0x0008000000000000)
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_INDEX UINT64_C(0x0007ff0000000000)
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_WQP UINT64_C(0x0000000fffffffff)
-#define POW_STATUS_LOAD_RESULT_PEND_WQP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3d" "PEND_SWITCH\0" \
- "b\x3c" "PEND_SWITCH_FULL\0" \
- "b\x3b" "PEND_SWITCH_NULL\0" \
- "b\x3a" "PEND_DESCHED\0" \
- "b\x39" "PEND_DESCHED_SWITCH\0" \
- "b\x38" "PEND_NOSCHED\0" \
- "b\x37" "PEND_NEW_WORK\0" \
- "b\x36" "PEND_NEW_WORK_WAIT\0" \
- "b\x35" "PEND_NULL_RD\0" \
- "b\x34" "PEND_NOSCHED_CLR\0" \
- "f\x28\x0b" "PEND_INDEX\0" \
- "f\x00\x24" "PEND_WQP\0"
/* get_cur = 1 and get_wqp = 0 and get_rev = 0 ("cur_tag_next") */
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -432,17 +398,6 @@
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAIL UINT64_C(0x0000000400000000)
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG_TYPE UINT64_C(0x0000000300000000)
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG UINT64_C(0x00000000ffffffff)
-#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x33\x0b" "LINK_INDEX\0" \
- "f\x28\x0b" "INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "b\x23" "HEAD\0" \
- "b\x22" "TAIL\0" \
- "f\x20\x02" "TAG_TYPE\0" \
- "f\x00\x20" "TAG\0"
/* get_cur = 1 and get_wqp = 0 and get_rev = 1 ("cur_tag_prev") */
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -453,17 +408,6 @@
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAIL UINT64_C(0x0000000400000000)
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG_TYPE UINT64_C(0x0000000300000000)
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG UINT64_C(0x00000000ffffffff)
-#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x33\x0b" "REVLINK_INDEX\0" \
- "f\x28\x0b" "INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "b\x23" "HEAD\0" \
- "b\x22" "TAIL\0" \
- "f\x20\x02" "TAG_TYPE\0" \
- "f\x00\x20" "TAG\0"
/* get_cur = 1 and get_wqp = 1 and get_rev = 0 ("cur_wqp_next") */
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -471,14 +415,6 @@
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_INDEX UINT64_C(0x0007ff0000000000)
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_GRP UINT64_C(0x000000f000000000)
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_WQP UINT64_C(0x0000000fffffffff)
-#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x33\x0b" "LINK_INDEX\0" \
- "f\x28\x0b" "INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "f\x00\x24" "WQP\0"
/* get_cur = 1 and get_wqp = 1 and get_rev = 1 ("cur_wqp_prev") */
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -486,14 +422,6 @@
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_INDEX UINT64_C(0x0007ff0000000000)
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_GRP UINT64_C(0x000000f000000000)
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_WQP UINT64_C(0x0000000fffffffff)
-#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x33\x0b" "REVLINK_INDEX\0" \
- "f\x28\x0b" "INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "f\x00\x24" "WQP\0"
/* pow memory load */
#define POW_OP_SUBDID_MEMORY_LOAD 2
@@ -510,28 +438,12 @@
#define POW_MEMORY_LOAD_RESULT_TAG_TAIL UINT64_C(0x0000000400000000)
#define POW_MEMORY_LOAD_RESULT_TAG_TAG_TYPE UINT64_C(0x0000000300000000)
#define POW_MEMORY_LOAD_RESULT_TAG_TAG UINT64_C(0x00000000ffffffff)
-#define POW_MEMORY_LOAD_RESULT_TAG_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x28\x0b" "NEXT_INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "b\x22" "TAIL\0" \
- "f\x20\x02" "TAG_TYPE\0" \
- "f\x00\x20" "TAG\0"
/* get_des = 0 and get_wqp = 1 ("wqp") */
#define POW_MEMORY_LOAD_RESULT_WQP_XXX_63_51 UINT64_C(0xfff8000000000000)
#define POW_MEMORY_LOAD_RESULT_WQP_NEXT_INDEX UINT64_C(0x0007ff0000000000)
#define POW_MEMORY_LOAD_RESULT_WQP_GRP UINT64_C(0x000000f000000000)
#define POW_MEMORY_LOAD_RESULT_WQP_WQP UINT64_C(0x0000000fffffffff)
-#define POW_MEMORY_LOAD_RESULT_WQP_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x28\x0b" "NEXT_INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "f\x00\x24" "WQP\0"
/* get_des = 1 ("desched") */
#define POW_MEMORY_LOAD_RESULT_DESCHED_XXX_63_51 UINT64_C(0xfff8000000000000)
@@ -541,16 +453,6 @@
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_SWITCH UINT64_C(0x0000000400000000)
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TYPE UINT64_C(0x0000000300000000)
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TAG UINT64_C(0x00000000ffffffff)
-#define POW_MEMORY_LOAD_RESULT_DESCHED_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x28\x0b" "FWD_INDEX\0" \
- "f\x24\x04" "GRP\0" \
- "b\x23" "NOSCHED\0" \
- "b\x22" "PEND_SWITCH\0" \
- "f\x20\x02" "PEND_TYPE\0" \
- "f\x00\x20" "PEND_TAG\0"
/* pow index/pointer load */
#define POW_OP_SUBDID_IDXPTR_LOAD 3
@@ -574,18 +476,6 @@
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_HEAD UINT64_C(0x00000000007ff000)
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_11 UINT64_C(0x0000000000000800)
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_TAIL UINT64_C(0x00000000000007ff)
-#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x33" "FREE_VAL\0" \
- "b\x32" "FREE_ONE\0" \
- "f\x26\x0b" "FREE_HEAD\0" \
- "f\x1a\x0b" "FREE_TAIL\0" \
- "b\x19" "LOC_VAL\0" \
- "b\x18" "LOC_ONE\0" \
- "f\x0c\x0b" "LOC_HEAD\0" \
- "f\x00\x0b" "LOC_TAIL\0"
/* get_rmt = 0 and get_des_get_tail = 1 ("desched") */
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_63_52 UINT64_C(0xfff0000000000000)
@@ -601,18 +491,6 @@
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_HEAD UINT64_C(0x00000000007ff000)
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_11 UINT64_C(0x0000000000000800)
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_TAIL UINT64_C(0x00000000000007ff)
-#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x33" "NOSCHED_VAL\0" \
- "b\x32" "NOSCHED_ONE\0" \
- "f\x26\x0b" "NOSCHED_HEAD\0" \
- "f\x1a\x0b" "NOSCHED_TAIL\0" \
- "b\x19" "DES_VAL\0" \
- "b\x18" "DES_ONE\0" \
- "f\x0c\x0b" "DES_HEAD\0" \
- "f\x00\x0b" "DES_TAIL\0"
/* get_rmt = 1 and get_des_get_tail = 0 ("remote_head") */
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_XXX_63_39 UINT64_C(0xffffff8000000000)
@@ -620,14 +498,6 @@
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_VAL UINT64_C(0x0000002000000000)
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_ONE UINT64_C(0x0000001000000000)
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_HEAD UINT64_C(0x0000000fffffffff)
-#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x26" "RMT_IS_HEAD\0" \
- "b\x25" "RMT_VAL\0" \
- "b\x24" "RMT_ONE\0" \
- "f\x00\x24" "RMT_HEAD\0"
/* get_rmt = 1 and get_des_get_tail = 1 ("remote_tail") */
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_XXX_63_39 UINT64_C(0xffffff8000000000)
@@ -635,14 +505,6 @@
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_VAL UINT64_C(0x0000002000000000)
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_ONE UINT64_C(0x0000001000000000)
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_TAIL UINT64_C(0x0000000fffffffff)
-#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x26" "RMT_IS_HEAD\0" \
- "b\x25" "RMT_VAL\0" \
- "b\x24" "RMT_ONE\0" \
- "f\x00\x24" "RMT_TAIL\0"
/* pow null rd */
#define POW_OP_SUBDID_NULL_RD 4
@@ -692,45 +554,18 @@
#define POW_WQE_WORD0_XXX_63_40 UINT64_C(0xffffff0000000000)
#define POW_WQE_WORD0_NEXT UINT64_C(0x000000ffffffffff)
-#define POW_WQE_WORD0_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x28" "NEXT\0"
#define POW_WQE_WORD1_XXX_63_42 UINT64_C(0xfffffc0000000000)
#define POW_WQE_WORD1_QOS UINT64_C(0x0000038000000000)
#define POW_WQE_WORD1_GRP UINT64_C(0x0000007800000000)
#define POW_WQE_WORD1_TT UINT64_C(0x0000000700000000)
#define POW_WQE_WORD1_TAG UINT64_C(0x00000000ffffffff)
-#define POW_WQE_WORD1_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x27\x03" "QOS\0" \
- "f\x23\x04" "GRP\0" \
- "f\x20\x03" "TT\0" \
- "f\x00\x20" "TAG\0"
/* ------------------------------------------------------------------------- */
-/* for snprintb(9) */
-
-#define POW_PP_GRP_MSKX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x10" "GRP_MSK\0"
#define POW_PP_GRP_MSK0_BITS POW_PP_GRP_MSKX_BITS
#define POW_PP_GRP_MSK1_BITS POW_PP_GRP_MSKX_BITS
-#define POW_WQ_INT_THRX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x1c" "TC_EN\0" \
- "f\x18\x04" "TC_THR\0" \
- "f\x0c\x06" "DS_THR\0" \
- "f\x00\x06" "IQ_THR\0"
+
#define POW_WQ_INT_THR0_BITS POW_WQ_INT_THRX_BITS
#define POW_WQ_INT_THR1_BITS POW_WQ_INT_THRX_BITS
#define POW_WQ_INT_THR2_BITS POW_WQ_INT_THRX_BITS
@@ -747,13 +582,7 @@
#define POW_WQ_INT_THR13_BITS POW_WQ_INT_THRX_BITS
#define POW_WQ_INT_THR14_BITS POW_WQ_INT_THRX_BITS
#define POW_WQ_INT_THR15_BITS POW_WQ_INT_THRX_BITS
-#define POW_WQ_INT_CNTX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x18\x04" "TC_CNT\0" \
- "f\x0c\x06" "DS_CNT\0" \
- "f\x00\x06" "IQ_CNT\0"
+
#define POW_WQ_INT_CNT0_BITS POW_WQ_INT_CNTX_BITS
#define POW_WQ_INT_CNT1_BITS POW_WQ_INT_CNTX_BITS
#define POW_WQ_INT_CNT2_BITS POW_WQ_INT_CNTX_BITS
@@ -770,15 +599,7 @@
#define POW_WQ_INT_CNT13_BITS POW_WQ_INT_CNTX_BITS
#define POW_WQ_INT_CNT14_BITS POW_WQ_INT_CNTX_BITS
#define POW_WQ_INT_CNT15_BITS POW_WQ_INT_CNTX_BITS
-#define POW_QOS_THRX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x30\x07" "DES_CNT\0" \
- "f\x24\x07" "BUF_CNT\0" \
- "f\x18\x07" "FREE_CNT\0" \
- "f\x0c\x06" "MAX_THR\0" \
- "f\x00\x06" "MIN_THR\0"
+
#define POW_QOS_THR0_BITS POW_QOS_THRX_BITS
#define POW_QOS_THR1_BITS POW_QOS_THRX_BITS
#define POW_QOS_THR2_BITS POW_QOS_THRX_BITS
@@ -787,14 +608,7 @@
#define POW_QOS_THR5_BITS POW_QOS_THRX_BITS
#define POW_QOS_THR6_BITS POW_QOS_THRX_BITS
#define POW_QOS_THR7_BITS POW_QOS_THRX_BITS
-#define POW_QOS_RNDX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x18\x08" "RND_P3\0" \
- "f\x10\x08" "RND_P2\0" \
- "f\x08\x08" "RND_P1\0" \
- "f\x00\x08" "RND\0"
+
#define POW_QOS_RND0_BITS POW_QOS_RNDX_BITS
#define POW_QOS_RND1_BITS POW_QOS_RNDX_BITS
#define POW_QOS_RND2_BITS POW_QOS_RNDX_BITS
@@ -803,45 +617,6 @@
#define POW_QOS_RND5_BITS POW_QOS_RNDX_BITS
#define POW_QOS_RND6_BITS POW_QOS_RNDX_BITS
#define POW_QOS_RND7_BITS POW_QOS_RNDX_BITS
-#define POW_WQ_INT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x10\x10" "IQ_DIS\0" \
- "f\x00\x10" "WQ_INT\0"
-#define POW_WQ_INT_PC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x1c" "PC\0" \
- "f\x08\x14" "PC_THR\0"
-#define POW_NW_TIM_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x0a" "NW_TIM\0"
-#define POW_ECC_ERR_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x0d" "IOP_IE\0" \
- "f\x10\x0d" "IOP\0" \
- "b\x0d" "RPE_IE\0" \
- "b\x0c" "RPE\0" \
- "f\x04\x05" "SYN\0" \
- "b\x03" "DBE_IE\0" \
- "b\x02" "SBE_IE\0" \
- "b\x01" "DBE\0" \
- "b\x00" "SBE\0"
-#define POW_NOS_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x07" "NOS_CNT\0"
-#define POW_WS_PCX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
#define POW_WS_PC0_BITS POW_WS_PCX_BITS
#define POW_WS_PC1_BITS POW_WS_PCX_BITS
@@ -859,10 +634,6 @@
#define POW_WS_PC13_BITS POW_WS_PCX_BITS
#define POW_WS_PC14_BITS POW_WS_PCX_BITS
#define POW_WS_PC15_BITS POW_WS_PCX_BITS
-#define POW_WA_PCX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
#define POW_WA_PC0_BITS POW_WA_PCX_BITS
#define POW_WA_PC1_BITS POW_WA_PCX_BITS
@@ -872,10 +643,6 @@
#define POW_WA_PC5_BITS POW_WA_PCX_BITS
#define POW_WA_PC6_BITS POW_WA_PCX_BITS
#define POW_WA_PC7_BITS POW_WA_PCX_BITS
-#define POW_IQ_CNTX_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
#define POW_IQ_CNT0_BITS POW_IQ_CNTX_BITS
#define POW_IQ_CNT1_BITS POW_IQ_CNTX_BITS
@@ -885,39 +652,5 @@
#define POW_IQ_CNT5_BITS POW_IQ_CNTX_BITS
#define POW_IQ_CNT6_BITS POW_IQ_CNTX_BITS
#define POW_IQ_CNT7_BITS POW_IQ_CNTX_BITS
-#define POW_WA_COM_PC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "WA_PC\0"
-#define POW_IQ_COM_CNT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
-
-#define POW_TS_PC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "TS_PC\0"
-#define POW_DS_PC_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x00\x20" "DS_PC\0"
-#define POW_BIST_STAT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x10" "PP\0" \
- "b\x08" "CAM\0" \
- "b\x07" "NBT1\0" \
- "b\x06" "NBT0\0" \
- "b\x05" "IDX\0" \
- "b\x04" "FIDX\0" \
- "b\x03" "NBR1\0" \
- "b\x02" "NBR0\0" \
- "b\x01" "PEND\0" \
- "b\x00" "ADR\0"
#endif /* _OCTEON_POWREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_twsireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_twsireg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_twsireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_twsireg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -113,56 +113,6 @@
#define TWSI_CTL_AAK UINT8_C(0x04)
#define TWSI_CTL_XXX_1_0 0x03
-/* TWSI Status Register */
-
-/* ---- snprintb */
-
-#define MIO_TWS_SW_TWSI_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x3f" "V\0" \
- "b\x3e" "SLONLY\0" \
- "b\x3d" "EIA\0" \
- "f\x39\x04" "OP\0" \
- "b\x38" "R\0" \
- "b\x37" "SOVR\0" \
- "f\x34\x03" "SIZE\0" \
- "f\x32\x02" "SCR\0" \
- "f\x28\x0a" "A\0" \
- "f\x23\x05" "IA\0" \
- "f\x20\x03" "EOP_IA\0" \
- "f\x00\x20" "D\0"
-
-#define MIO_TWS_TWSI_SW_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x3e\x02" "V\0" \
- "f\x00\x20" "D\0"
-
-#define MIO_TWS_INT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x0b" "SCL\0" \
- "b\x0a" "SDA\0" \
- "b\x09" "SCL_OVR\0" \
- "b\x08" "SDA_OVR\0" \
- "b\x06" "CORE_EN\0" \
- "b\x05" "TS_EN\0" \
- "b\x04" "ST_EN\0" \
- "b\x02" "CORE_INT\0" \
- "b\x01" "TS_INT\0" \
- "b\x00" "ST_INT\0"
-
-#define MIO_TWS_SW_TWSI_EXT_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x20\x08" "IA\0" \
- "f\x00\x20" "D\0"
-
/* ---- bus_space */
#define MIO_TWS_NUNITS 1
Index: src/sys/arch/mips/cavium/dev/octeon_pip.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pip.c:1.6 src/sys/arch/mips/cavium/dev/octeon_pip.c:1.7
--- src/sys/arch/mips/cavium/dev/octeon_pip.c:1.6 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pip.c Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pip.c,v 1.6 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_pip.c,v 1.7 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.6 2020/06/22 02:26:20 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.7 2020/06/22 03:05:07 simonb Exp $");
#include "opt_octeon.h"
@@ -42,47 +42,6 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_pip.c
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_pipvar.h>
-/*
- * register definitions (for debug and statics)
- */
-#define _ENTRY(x) { #x, x##_BITS, x##_OFFSET }
-#define _ENTRY_0_3(x) \
- _ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x## 3)
-#define _ENTRY_0_7(x) \
- _ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x## 3), \
- _ENTRY(x## 4), _ENTRY(x## 5), _ENTRY(x## 6), _ENTRY(x## 7)
-#define _ENTRY_0_1_2_32(x) \
- _ENTRY(x## 0), _ENTRY(x## 1), _ENTRY(x## 2), _ENTRY(x##32)
-
-struct octpip_dump_reg_ {
- const char *name;
- const char *format;
- size_t offset;
-};
-
-static const struct octpip_dump_reg_ octpip_dump_stats_[] = {
-/* PIP_QOS_DIFF[0-63] */
- _ENTRY_0_1_2_32 (PIP_STAT0_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT1_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT2_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT3_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT4_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT5_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT6_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT7_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT8_PRT),
- _ENTRY_0_1_2_32 (PIP_STAT9_PRT),
-/* PIP_TAG_INC[0-63] */
- _ENTRY_0_1_2_32 (PIP_STAT_INB_PKTS),
- _ENTRY_0_1_2_32 (PIP_STAT_INB_OCTS),
- _ENTRY_0_1_2_32 (PIP_STAT_INB_ERRS),
-};
-
-#undef _ENTRY
-#undef _ENTRY_0_3
-#undef _ENTRY_0_7
-#undef _ENTRY_0_1_2_32
-
/* XXX */
void
octpip_init(struct octpip_attach_args *aa, struct octpip_softc **rsc)
@@ -187,7 +146,6 @@ octpip_prt_cfg_enable(struct octpip_soft
void
octpip_stats(struct octpip_softc *sc, struct ifnet *ifp, int gmx_port)
{
- const struct octpip_dump_reg_ *reg;
uint64_t tmp, pkts;
uint64_t pip_stat_ctl;
@@ -202,8 +160,7 @@ octpip_stats(struct octpip_softc *sc, st
pip_stat_ctl = _PIP_RD8(sc, PIP_STAT_CTL_OFFSET);
_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl | PIP_STAT_CTL_RDCLR);
- reg = &octpip_dump_stats_[gmx_port];
- tmp = _PIP_RD8(sc, reg->offset);
+ tmp = _PIP_RD8(sc, PIP_STAT0_PRT_OFFSET(gmx_port));
pkts = __SHIFTOUT(tmp, PIP_STAT0_PRTN_DRP_PKTS);
if_statadd(ifp, if_iqdrops, pkts);
Index: src/sys/arch/mips/cavium/dev/octeon_rnmreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.4 src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.4 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_rnmreg.h Mon Jun 22 03:05:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_rnmreg.h,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_rnmreg.h,v 1.5 2020/06/22 03:05:07 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -56,26 +56,6 @@
#define RNM_BIST_STATUS_RRC UINT64_C(0x0000000000000002)
#define RNM_BIST_STATUS_MEM UINT64_C(0x0000000000000001)
-/* ---- snprintb */
-
-#define RNM_CTL_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "f\x05\x04" "ENT_SEL\0" \
- "b\x04" "EXP_ENT\0" \
- "b\x03" "RNG_RST\0" \
- "b\x02" "RNM_RST\0" \
- "b\x01" "RNG_EN\0" \
- "b\x00" "ENT_EN\0"
-
-#define RNM_BIST_STATUS_BITS \
- "\177" /* new format */ \
- "\020" /* hex display */ \
- "\020" /* %016x format */ \
- "b\x01" "RRC\0" \
- "b\x00" "MEM\0"
-
/* ---- bus_space */
#define RNM_BASE 0x0001180040000000ULL
