Module Name: src
Committed By: simonb
Date: Tue Jun 23 05:18:02 UTC 2020
Modified Files:
src/sys/arch/evbmips/conf: ERLITE
src/sys/arch/mips/cavium: octeon1p_iobus.c
src/sys/arch/mips/cavium/dev: octeon_pip.c octeon_pipreg.h
octeon_pipvar.h octeon_smi.c octeon_smireg.h octeon_smivar.h
Log Message:
Redo cnmac attachments - cnmacM @ gmxN @ pip0 @ iobus
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/evbmips/conf/ERLITE
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/octeon1p_iobus.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/cavium/dev/octeon_pip.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_pipreg.h \
src/sys/arch/mips/cavium/dev/octeon_pipvar.h \
src/sys/arch/mips/cavium/dev/octeon_smi.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/cavium/dev/octeon_smireg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/cavium/dev/octeon_smivar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/conf/ERLITE
diff -u src/sys/arch/evbmips/conf/ERLITE:1.26 src/sys/arch/evbmips/conf/ERLITE:1.27
--- src/sys/arch/evbmips/conf/ERLITE:1.26 Fri Jun 5 07:17:38 2020
+++ src/sys/arch/evbmips/conf/ERLITE Tue Jun 23 05:18:02 2020
@@ -1,11 +1,11 @@
-# $NetBSD: ERLITE,v 1.26 2020/06/05 07:17:38 simonb Exp $
+# $NetBSD: ERLITE,v 1.27 2020/06/23 05:18:02 simonb Exp $
include "arch/mips/conf/std.octeon"
include "arch/evbmips/conf/files.octeon"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "ERLITE-$Revision: 1.26 $"
+#ident "ERLITE-$Revision: 1.27 $"
maxusers 32
@@ -116,12 +116,16 @@ bootbus0 at mainbus?
com* at iobus?
-octrnm* at iobus?
+octsmi* at iobus? # MDIO controller
+octpip* at iobus? # PIP packet processing controller
-octgmx* at iobus?
+octgmx* at octpip?
cnmac* at octgmx?
+octrnm* at iobus? # Random Number Memory (and generator)
+
dwctwo* at iobus?
+
usb* at dwctwo?
uhub* at usb?
@@ -131,6 +135,7 @@ umass* at uhub? port ? configuration ?
scsibus* at umass? channel ?
sd* at scsibus? target ? lun ? # SCSI disk drives
+# Ethernet PHYs
atphy* at mii? phy ? # Attansic/Atheros PHYs
ukphy* at mii? phy ? # generic unknown PHYs
@@ -173,4 +178,3 @@ pseudo-device drvctl # driver control
include "dev/veriexec.config"
cinclude "arch/evbmips/conf/ERLITE.local"
-
Index: src/sys/arch/mips/cavium/octeon1p_iobus.c
diff -u src/sys/arch/mips/cavium/octeon1p_iobus.c:1.4 src/sys/arch/mips/cavium/octeon1p_iobus.c:1.5
--- src/sys/arch/mips/cavium/octeon1p_iobus.c:1.4 Sun May 31 14:05:21 2020
+++ src/sys/arch/mips/cavium/octeon1p_iobus.c Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon1p_iobus.c,v 1.4 2020/05/31 14:05:21 simonb Exp $ */
+/* $NetBSD: octeon1p_iobus.c,v 1.5 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon1p_iobus.c,v 1.4 2020/05/31 14:05:21 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon1p_iobus.c,v 1.5 2020/06/23 05:18:02 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -41,7 +41,6 @@ __KERNEL_RCSID(0, "$NetBSD: octeon1p_iob
#include <mips/cavium/include/iobusvar.h>
/* ---- UART */
-
#include <mips/cavium/dev/octeon_uartreg.h>
static const struct iobus_unit iobus_units_octuart[] = {
{
@@ -59,7 +58,6 @@ static const struct iobus_dev iobus_dev_
};
/* ---- RNM */
-
#include <mips/cavium/dev/octeon_rnmreg.h>
static const struct iobus_unit iobus_units_octrnm[] = {
{
@@ -74,7 +72,6 @@ static const struct iobus_dev iobus_dev_
};
/* ---- TWSI */
-
#include <mips/cavium/dev/octeon_twsireg.h>
static const struct iobus_unit iobus_units_octtwsi[] = {
{
@@ -89,7 +86,6 @@ static const struct iobus_dev iobus_dev_
};
/* ---- MPI/SPI */
-
#include <mips/cavium/dev/octeon_mpireg.h>
static const struct iobus_unit iobus_units_octmpi[] = {
{
@@ -102,19 +98,33 @@ static const struct iobus_dev iobus_dev_
.nunits = MPI_NUNITS,
.units = iobus_units_octmpi
};
-/* ---- GMX */
-#include <mips/cavium/dev/octeon_gmxreg.h>
-static const struct iobus_unit iobus_units_octgmx[] = {
+/* ---- SMI */
+#include <mips/cavium/dev/octeon_smireg.h>
+static const struct iobus_unit iobus_units_octsmi[] = {
+ {
+ .addr = SMI_BASE
+ }
+};
+
+static const struct iobus_dev iobus_dev_octsmi = {
+ .name = "octsmi",
+ .nunits = SMI_NUNITS,
+ .units = iobus_units_octsmi
+};
+
+/* ---- PIP */
+#include <mips/cavium/dev/octeon_pipreg.h>
+static const struct iobus_unit iobus_units_octpip[] = {
{
- .addr = GMX0_BASE_IF0
+ .addr = PIP_BASE
}
};
-static const struct iobus_dev iobus_dev_octgmx = {
- .name = "octgmx",
- .nunits = GMX_IF_NUNITS,
- .units = iobus_units_octgmx
+static const struct iobus_dev iobus_dev_octpip = {
+ .name = "octpip",
+ .nunits = 1,
+ .units = iobus_units_octpip
};
@@ -139,7 +149,8 @@ const struct iobus_dev * const iobus_dev
&iobus_dev_octrnm,
&iobus_dev_octtwsi,
&iobus_dev_octmpi,
- &iobus_dev_octgmx,
+ &iobus_dev_octsmi,
+ &iobus_dev_octpip,
&iobus_dev_octusbn,
};
Index: src/sys/arch/mips/cavium/dev/octeon_pip.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pip.c:1.7 src/sys/arch/mips/cavium/dev/octeon_pip.c:1.8
--- src/sys/arch/mips/cavium/dev/octeon_pip.c:1.7 Mon Jun 22 03:05:07 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pip.c Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pip.c,v 1.7 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_pip.c,v 1.8 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,9 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.7 2020/06/22 03:05:07 simonb Exp $");
-
-#include "opt_octeon.h"
+__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.8 2020/06/23 05:18:02 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -37,10 +35,68 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_pip.c
#include <sys/syslog.h>
#include <sys/time.h>
#include <net/if.h>
+
#include <mips/locore.h>
+
#include <mips/cavium/octeonvar.h>
+#include <mips/cavium/dev/octeon_gmxreg.h>
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_pipvar.h>
+#include <mips/cavium/include/iobusvar.h>
+
+static int octpip_match(device_t, struct cfdata *, void *);
+static void octpip_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(octpip, sizeof(struct octpip_softc),
+ octpip_match, octpip_attach, NULL, NULL);
+
+static int
+octpip_match(device_t parent, struct cfdata *cf, void *aux)
+{
+ struct iobus_attach_args *aa = aux;
+
+ if (strcmp(cf->cf_name, aa->aa_name) != 0)
+ return 0;
+ return 1;
+}
+
+static void
+octpip_attach(device_t parent, device_t self, void *aux)
+{
+ struct octpip_softc *sc = device_private(self);
+ struct iobus_attach_args *aa = aux;
+ struct iobus_attach_args gmxaa;
+ struct iobus_unit gmxiu;
+ int i, ndevs;
+
+ sc->sc_dev = self;
+
+ aprint_normal("\n");
+
+ /*
+ * XXX: In a non-FDT world, should allow for the configuration
+ * of multple GMX devices.
+ */
+ ndevs = 1;
+
+ for (i = 0; i < ndevs; i++) {
+ memcpy(&gmxaa, aa, sizeof(gmxaa));
+ memset(&gmxiu, 0, sizeof(gmxiu));
+
+ gmxaa.aa_name = "octgmx";
+ gmxaa.aa_unitno = i;
+ gmxaa.aa_unit = &gmxiu;
+ gmxaa.aa_bust = aa->aa_bust;
+ gmxaa.aa_dmat = aa->aa_dmat;
+
+ if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) == MIPS_CN68XX)
+ gmxiu.addr = GMX_CN68XX_BASE_PORT(i, 0);
+ else
+ gmxiu.addr = GMX_BASE_PORT(i, 0);
+
+ config_found(self, &gmxaa, NULL);
+ }
+}
/* XXX */
void
@@ -90,10 +146,10 @@ octpip_port_config(struct octpip_softc *
}
/* RAWDRP=0; don't allow raw packet drop */
/* TAGINC=0 */
- SET(prt_cfg, PIP_PRT_CFGN_DYN_RS);
+ /* DYN_RS=0; disable dynamic short buffering */
/* INST_HDR=0 */
/* GRP_WAT=0 */
- SET(prt_cfg, (sc->sc_port << 24) & PIP_PRT_CFGN_QOS);
+ SET(prt_cfg, __SHIFTIN(sc->sc_port, PIP_PRT_CFGN_QOS));
/* QOS_WAT=0 */
/* SPARE=0 */
/* QOS_DIFF=0 */
@@ -153,7 +209,7 @@ octpip_stats(struct octpip_softc *sc, st
panic("%s: invalid argument. sc=%p, ifp=%p\n", __func__,
sc, ifp);
- if (gmx_port < 0 || gmx_port > 2) {
+ if (gmx_port < 0 || gmx_port > GMX_PORT_NUNITS) {
printf("%s: invalid gmx_port %d\n", __func__, gmx_port);
return;
}
Index: src/sys/arch/mips/cavium/dev/octeon_pipreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.4 src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.4 Mon Jun 22 12:26:11 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pipreg.h Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipreg.h,v 1.4 2020/06/22 12:26:11 simonb Exp $ */
+/* $NetBSD: octeon_pipreg.h,v 1.5 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -80,6 +80,7 @@
#define PIP_QOS_DIFF0 0x00011800a0000600ULL
/* PIP_QOS_DIFF[1-63] */
/* PIP_STAT[0-9]_PRT{0,1,2,32} */
+#define PIP_STAT0_PRT(i) (0x00011800a0000800ULL + (i) * 0x50)
#define PIP_STAT0_PRT0 0x00011800a0000800ULL
#define PIP_STAT0_PRT1 0x00011800a0000850ULL
#define PIP_STAT0_PRT2 0x00011800a00008a0ULL
@@ -275,7 +276,7 @@
#define PIP_GBL_CFG_15_11 UINT64_C(0x000000000000f800)
#define PIP_GBL_CFG_RAW_SHF UINT64_C(0x0000000000000700)
#define PIP_GBL_CFG_7_3 UINT64_C(0x00000000000000f8)
-#define PIP_GBL_CFG_NIP_SHF UINT64_C(0x0000000000000007)
+#define PIP_GBL_CFG_NIP_SHF_MASK UINT64_C(0x0000000000000007)
/*
* PIP_SFT_RST
@@ -576,51 +577,46 @@
#define PIP_WQE_WORD3_ADDR UINT64_C(0x000000ffffffffff)
/* opcode for WORD2[LE] */
-#define PIP_WQE_WORD2_LE_OPCODE_MAL 1ULL
-#define PIP_WQE_WORD2_LE_OPCODE_CSUM 2ULL
-#define PIP_WQE_WORD2_LE_OPCODE_UDPLEN 3ULL
-#define PIP_WQE_WORD2_LE_OPCODE_PORT 4ULL
-#define PIP_WQE_WORD2_LE_OPCODE_XXX_5 5ULL
-#define PIP_WQE_WORD2_LE_OPCODE_XXX_6 6ULL
-#define PIP_WQE_WORD2_LE_OPCODE_XXX_7 7ULL
-#define PIP_WQE_WORD2_LE_OPCODE_FINO 8ULL
-#define PIP_WQE_WORD2_LE_OPCODE_NOFL 9ULL
-#define PIP_WQE_WORD2_LE_OPCODE_FINRST 10ULL
-#define PIP_WQE_WORD2_LE_OPCODE_SYNURG 11ULL
-#define PIP_WQE_WORD2_LE_OPCODE_SYNRST 12ULL
-#define PIP_WQE_WORD2_LE_OPCODE_SYNFIN 13ULL
+#define PIP_WQE_WORD2_LE_OPCODE_MAL 1
+#define PIP_WQE_WORD2_LE_OPCODE_CSUM 2
+#define PIP_WQE_WORD2_LE_OPCODE_UDPLEN 3
+#define PIP_WQE_WORD2_LE_OPCODE_PORT 4
+#define PIP_WQE_WORD2_LE_OPCODE_XXX_5 5
+#define PIP_WQE_WORD2_LE_OPCODE_XXX_6 6
+#define PIP_WQE_WORD2_LE_OPCODE_XXX_7 7
+#define PIP_WQE_WORD2_LE_OPCODE_FINO 8
+#define PIP_WQE_WORD2_LE_OPCODE_NOFL 9
+#define PIP_WQE_WORD2_LE_OPCODE_FINRST 10
+#define PIP_WQE_WORD2_LE_OPCODE_SYNURG 11
+#define PIP_WQE_WORD2_LE_OPCODE_SYNRST 12
+#define PIP_WQE_WORD2_LE_OPCODE_SYNFIN 13
/* opcode for WORD2[IE] */
-#define PIP_WQE_WORD2_IE_OPCODE_NOTIP 1ULL
-#define PIP_WQE_WORD2_IE_OPCODE_CSUM 2ULL
-#define PIP_WQE_WORD2_IE_OPCODE_MALHDR 3ULL
-#define PIP_WQE_WORD2_IE_OPCODE_MAL 4ULL
-#define PIP_WQE_WORD2_IE_OPCODE_TTL 5ULL
-#define PIP_WQE_WORD2_IE_OPCODE_OPT 6ULL
+#define PIP_WQE_WORD2_IE_OPCODE_NOTIP 1
+#define PIP_WQE_WORD2_IE_OPCODE_CSUM 2
+#define PIP_WQE_WORD2_IE_OPCODE_MALHDR 3
+#define PIP_WQE_WORD2_IE_OPCODE_MAL 4
+#define PIP_WQE_WORD2_IE_OPCODE_TTL 5
+#define PIP_WQE_WORD2_IE_OPCODE_OPT 6
/* opcode for WORD2[RE] */
-#define PIP_WQE_WORD2_RE_OPCODE_PARTIAL 1ULL
-#define PIP_WQE_WORD2_RE_OPCODE_JABBER 2ULL
-#define PIP_WQE_WORD2_RE_OPCODE_OVRRUN 3ULL
-#define PIP_WQE_WORD2_RE_OPCODE_OVRSZ 4ULL
-#define PIP_WQE_WORD2_RE_OPCODE_ALIGN 5ULL
-#define PIP_WQE_WORD2_RE_OPCODE_FRAG 6ULL
-#define PIP_WQE_WORD2_RE_OPCODE_GMXFCS 7ULL
-#define PIP_WQE_WORD2_RE_OPCODE_UDRSZ 8ULL
-#define PIP_WQE_WORD2_RE_OPCODE_EXTEND 9ULL
-#define PIP_WQE_WORD2_RE_OPCODE_LENGTH 10ULL
-#define PIP_WQE_WORD2_RE_OPCODE_MIIRX 11ULL
-#define PIP_WQE_WORD2_RE_OPCODE_MIISKIP 12ULL
-#define PIP_WQE_WORD2_RE_OPCODE_MIINBL 13ULL
-#define PIP_WQE_WORD2_RE_OPCODE_XXX_14 14ULL
-#define PIP_WQE_WORD2_RE_OPCODE_XXX_15 15ULL
-#define PIP_WQE_WORD2_RE_OPCODE_XXX_16 16ULL
-#define PIP_WQE_WORD2_RE_OPCODE_SKIP 17ULL
-#define PIP_WQE_WORD2_RE_OPCODE_L2MAL 18ULL
-
-/* XXX backward compatibility */
-#define PIP_OVER_ERR PIP_WQE_WORD2_RE_OPCODE_OVRRUN
-#define PIP_GMX_FCS_ERR PIP_WQE_WORD2_RE_OPCODE_GMXFCS
-#define PIP_ALIGN_ERR PIP_WQE_WORD2_RE_OPCODE_ALIGN
+#define PIP_WQE_WORD2_RE_OPCODE_PARTIAL 1
+#define PIP_WQE_WORD2_RE_OPCODE_JABBER 2
+#define PIP_WQE_WORD2_RE_OPCODE_OVRRUN 3
+#define PIP_WQE_WORD2_RE_OPCODE_OVRSZ 4
+#define PIP_WQE_WORD2_RE_OPCODE_ALIGN 5
+#define PIP_WQE_WORD2_RE_OPCODE_FRAG 6
+#define PIP_WQE_WORD2_RE_OPCODE_GMXFCS 7
+#define PIP_WQE_WORD2_RE_OPCODE_UDRSZ 8
+#define PIP_WQE_WORD2_RE_OPCODE_EXTEND 9
+#define PIP_WQE_WORD2_RE_OPCODE_LENGTH 10
+#define PIP_WQE_WORD2_RE_OPCODE_MIIRX 11
+#define PIP_WQE_WORD2_RE_OPCODE_MIISKIP 12
+#define PIP_WQE_WORD2_RE_OPCODE_MIINBL 13
+#define PIP_WQE_WORD2_RE_OPCODE_XXX_14 14
+#define PIP_WQE_WORD2_RE_OPCODE_XXX_15 15
+#define PIP_WQE_WORD2_RE_OPCODE_XXX_16 16
+#define PIP_WQE_WORD2_RE_OPCODE_SKIP 17
+#define PIP_WQE_WORD2_RE_OPCODE_L2MAL 18
#endif /* _OCTEON_PIPREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_pipvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.4 Mon Jun 22 02:26:20 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pipvar.h Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipvar.h,v 1.4 2020/06/22 02:26:20 simonb Exp $ */
+/* $NetBSD: octeon_pipvar.h,v 1.5 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -32,6 +32,7 @@
/* XXX */
struct octpip_softc {
+ device_t sc_dev;
int sc_port;
bus_space_tag_t sc_regt;
bus_space_handle_t sc_regh;
Index: src/sys/arch/mips/cavium/dev/octeon_smi.c
diff -u src/sys/arch/mips/cavium/dev/octeon_smi.c:1.4 src/sys/arch/mips/cavium/dev/octeon_smi.c:1.5
--- src/sys/arch/mips/cavium/dev/octeon_smi.c:1.4 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_smi.c Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_smi.c,v 1.5 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,12 +27,15 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.5 2020/06/23 05:18:02 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/mbuf.h>
+
#include <mips/locore.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_fpareg.h>
@@ -40,38 +43,85 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_smireg.h>
#include <mips/cavium/dev/octeon_smivar.h>
+#include <mips/cavium/include/iobusvar.h>
-static void octsmi_enable(struct octsmi_softc *);
+/*
+ * System Management Interface
+ *
+ *
+ * CN30XX - 1 SMI interface
+ * CN31XX - 1 SMI interface
+ * CN38XX - 1 SMI interface
+ * CN50XX - 1 SMI interface
+ * CN52XX - 2 SMI interfaces
+ * CN56XX - 2 SMI interfaces
+ * CN58XX - 1 SMI interface
+ * CN61XX - 2 SMI interfaces
+ * CN63XX - 2 SMI interfaces
+ * CN66XX - 2 SMI interfaces
+ * CN68XX - 4 SMI interfaces
+ * CN70XX - 2 SMI interfaces
+ * CN73XX - 2 SMI interfaces
+ * CN78XX - 4 SMI interfaces
+ * CNF71XX - 2 SMI interfaces
+ * CNF75XX - 2 SMI interfaces
+ */
+
+static int octsmi_match(device_t, struct cfdata *, void *);
+static void octsmi_attach(device_t, device_t, void *);
+
+struct octsmi_softc *smi_list; /* XXX up to 4 SMIs on CN68XX,CN78XX */
+
+#define _SMI_RD8(sc, off) \
+ bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
+#define _SMI_WR8(sc, off, v) \
+ bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
+
+CFATTACH_DECL_NEW(octsmi, sizeof(struct octsmi_softc),
+ octsmi_match, octsmi_attach, NULL, NULL);
+
+static int
+octsmi_match(device_t parent, struct cfdata *cf, void *aux)
+{
+ struct iobus_attach_args *aa = aux;
+
+ if (strcmp(cf->cf_name, aa->aa_name) != 0)
+ return 0;
+ if (aa->aa_unitno < SMI_NUNITS)
+ return 1;
+ else
+ return 0;
+}
-/* XXX */
-void
-octsmi_init(struct octsmi_attach_args *aa, struct octsmi_softc **rsc)
+static void
+octsmi_attach(device_t parent, device_t self, void *aux)
{
- struct octsmi_softc *sc;
+ struct octsmi_softc *sc = device_private(self);
+ struct iobus_attach_args *aa = aux;
int status;
- sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
- if (sc == NULL)
- panic("can't allocate memory: %s", __func__);
+ sc->sc_dev = self;
+ sc->sc_regt = aa->aa_bust;
- sc->sc_port = aa->aa_port;
- sc->sc_regt = aa->aa_regt;
+ aprint_normal("\n");
- status = bus_space_map(sc->sc_regt, SMI_BASE, SMI_SIZE, 0,
+ status = bus_space_map(sc->sc_regt, aa->aa_unit->addr, SMI_SIZE, 0,
&sc->sc_regh);
- if (status != 0)
- panic("can't map %s space", "smi register");
+ if (status != 0) {
+ aprint_error_dev(self, "could not map registers\n");
+ return;
+ }
- octsmi_enable(sc);
+ smi_list = sc;
- *rsc = sc;
+ const uint64_t magic_value =
+ SMI_CLK_PREAMBLE |
+ __SHIFTIN(0x4, SMI_CLK_SAMPLE) | /* XXX magic 0x4 */
+ __SHIFTIN(0x64, SMI_CLK_PHASE); /* XXX magic 0x64 */
+ _SMI_WR8(sc, SMI_CLK_OFFSET, magic_value);
+ _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
}
-#define _SMI_RD8(sc, off) \
- bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
-#define _SMI_WR8(sc, off, v) \
- bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
-
int
octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val)
{
@@ -119,27 +169,27 @@ octsmi_write(struct octsmi_softc *sc, in
smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
if (timo-- == 0) {
- /* XXX log */
- printf("ERROR: cnmac_mii_writereg(0x%x, 0x%x, 0x%hx) "
- "timed out.\n", phy_addr, reg, value);
return ETIMEDOUT;
}
delay(10);
smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
}
+ if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) {
+ /* XXX log */
+ printf("ERROR: octsmi_write(0x%x, 0x%x, 0x%hx) timed out.\n",
+ phy_addr, reg, value);
+ }
return 0;
}
-static void
-octsmi_enable(struct octsmi_softc *sc)
+struct octsmi_softc *
+octsmi_lookup(int phandle, int port)
{
- _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN);
-}
+ struct octsmi_softc *smi;
-void
-octsmi_set_clock(struct octsmi_softc *sc, uint64_t clock)
-{
- _SMI_WR8(sc, SMI_CLK_OFFSET, clock);
-}
+ /* XXX deal with more than one SMI ... */
+ smi = smi_list;
+ return smi;
+}
Index: src/sys/arch/mips/cavium/dev/octeon_smireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.2 src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.2 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_smireg.h Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_smireg.h,v 1.3 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -33,26 +33,22 @@
#ifndef _OCTEON_SMIREG_H_
#define _OCTEON_SMIREG_H_
-#define SMI_CMD 0x0001180000001800ULL
-#define SMI_WR_DAT 0x0001180000001808ULL
-#define SMI_RD_DAT 0x0001180000001810ULL
-#define SMI_CLK 0x0001180000001818ULL
-#define SMI_EN 0x0001180000001820ULL
-
-#define SMI_CMD_OFFSET 0x00ULL
-#define SMI_WR_DAT_OFFSET 0x08ULL
-#define SMI_RD_DAT_OFFSET 0x10ULL
-#define SMI_CLK_OFFSET 0x18ULL
-#define SMI_EN_OFFSET 0x20ULL
-
-#define SMI_BASE 0x0001180000001800ULL
-#define SMI_SIZE 0x028ULL
+#define SMI_CMD_OFFSET 0x00ULL
+#define SMI_WR_DAT_OFFSET 0x08ULL
+#define SMI_RD_DAT_OFFSET 0x10ULL
+#define SMI_CLK_OFFSET 0x18ULL
+#define SMI_EN_OFFSET 0x20ULL
+
+#define SMI_BASE 0x0001180000001800ULL
+#define SMI_SIZE 0x040ULL
+/* XXX - support 1 SMI unit for direct attach; some CPUs have 4 SMIs */
+#define SMI_NUNITS 1
/* SMI CMD */
#define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000)
#define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000)
-#define SMI_CMD_PHY_OP_READ 1
-#define SMI_CMD_PHY_OP_WRITE 0
+#define SMI_CMD_PHY_OP_READ 1
+#define SMI_CMD_PHY_OP_WRITE 0
#define SMI_CMD_15_13 UINT64_C(0x000000000000e000)
#define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00)
#define SMI_CMD_7_5 UINT64_C(0x00000000000000e0)
Index: src/sys/arch/mips/cavium/dev/octeon_smivar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.5 src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.6
--- src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.5 Thu Jun 18 13:52:08 2020
+++ src/sys/arch/mips/cavium/dev/octeon_smivar.h Tue Jun 23 05:18:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smivar.h,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
+/* $NetBSD: octeon_smivar.h,v 1.6 2020/06/23 05:18:02 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -31,20 +31,15 @@
/* XXX */
struct octsmi_softc {
+ device_t sc_dev;
int sc_port;
bus_space_tag_t sc_regt;
bus_space_handle_t sc_regh;
};
-/* XXX */
-struct octsmi_attach_args {
- int aa_port;
- bus_space_tag_t aa_regt;
-};
-
-void octsmi_init(struct octsmi_attach_args *, struct octsmi_softc **);
int octsmi_read(struct octsmi_softc *, int, int, uint16_t *);
int octsmi_write(struct octsmi_softc *, int, int, uint16_t);
-void octsmi_set_clock(struct octsmi_softc *, uint64_t);
+struct octsmi_softc
+ *octsmi_lookup(int, int);
#endif /* _OCTEON_SMIVAR_H_ */
