Module Name: src Committed By: msaitoh Date: Tue Jun 23 14:36:00 UTC 2020
Modified Files: src/sys/dev/mii: miidevs.h miidevs_data.h Log Message: Regen. To generate a diff of this commit: cvs rdiff -u -r1.164 -r1.165 src/sys/dev/mii/miidevs.h cvs rdiff -u -r1.152 -r1.153 src/sys/dev/mii/miidevs_data.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/mii/miidevs.h diff -u src/sys/dev/mii/miidevs.h:1.164 src/sys/dev/mii/miidevs.h:1.165 --- src/sys/dev/mii/miidevs.h:1.164 Wed Apr 8 03:01:28 2020 +++ src/sys/dev/mii/miidevs.h Tue Jun 23 14:35:59 2020 @@ -1,10 +1,10 @@ -/* $NetBSD: miidevs.h,v 1.164 2020/04/08 03:01:28 msaitoh Exp $ */ +/* $NetBSD: miidevs.h,v 1.165 2020/06/23 14:35:59 msaitoh Exp $ */ /* * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * NetBSD: miidevs,v 1.167 2020/04/08 03:01:05 msaitoh Exp + * NetBSD: miidevs,v 1.168 2020/06/23 14:35:36 msaitoh Exp */ /*- @@ -630,8 +630,28 @@ #define MII_STR_xxVITESSE_VSC8601 "VSC8601 10/100/1000 PHY" #define MII_MODEL_xxVITESSE_VSC8641 0x0003 #define MII_STR_xxVITESSE_VSC8641 "Vitesse VSC8641 10/100/1000TX PHY" +#define MII_MODEL_xxVITESSE_VSC8504 0x000c +#define MII_STR_xxVITESSE_VSC8504 "Vitesse VSC8504 quad 10/100/1000TX PHY" +#define MII_MODEL_xxVITESSE_VSC8552 0x000e +#define MII_STR_xxVITESSE_VSC8552 "Vitesse VSC8552 dual 10/100/1000TX PHY" +#define MII_MODEL_xxVITESSE_VSC8502 0x0012 +#define MII_STR_xxVITESSE_VSC8502 "Vitesse VSC8502 dual 10/100/1000TX PHY" #define MII_MODEL_xxVITESSE_VSC8501 0x0013 #define MII_STR_xxVITESSE_VSC8501 "Vitesse VSC8501 10/100/1000TX PHY" +#define MII_MODEL_xxVITESSE_VSC8531 0x0017 +#define MII_STR_xxVITESSE_VSC8531 "Vitesse VSC8531 10/100/1000TX PHY" +#define MII_MODEL_xxVITESSE_VSC8662 0x0026 +#define MII_STR_xxVITESSE_VSC8662 "Vitesse VSC866[24] dual/quad 1000T 100FX 1000X PHY" +#define MII_MODEL_xxVITESSE_VSC8514 0x0027 +#define MII_STR_xxVITESSE_VSC8514 "Vitesse VSC8514 quad 1000T PHY" +#define MII_MODEL_xxVITESSE_VSC8512 0x002e +#define MII_STR_xxVITESSE_VSC8512 "Vitesse VSC8512 12port 1000T PHY" +#define MII_MODEL_xxVITESSE_VSC8522 0x002f +#define MII_STR_xxVITESSE_VSC8522 "Vitesse VSC8522 12port 1000T PHY" +#define MII_MODEL_xxVITESSE_VSC8658 0x0035 +#define MII_STR_xxVITESSE_VSC8658 "Vitesse VSC8658 octal 1000T 100FX 1000X PHY" +#define MII_MODEL_xxVITESSE_VSC8541 0x0037 +#define MII_STR_xxVITESSE_VSC8541 "Vitesse VSC8541 1000T PHY" /* XaQti Corp. PHYs */ #define MII_MODEL_xxXAQTI_XMACII 0x0000 Index: src/sys/dev/mii/miidevs_data.h diff -u src/sys/dev/mii/miidevs_data.h:1.152 src/sys/dev/mii/miidevs_data.h:1.153 --- src/sys/dev/mii/miidevs_data.h:1.152 Wed Apr 8 03:01:28 2020 +++ src/sys/dev/mii/miidevs_data.h Tue Jun 23 14:35:59 2020 @@ -1,10 +1,10 @@ -/* $NetBSD: miidevs_data.h,v 1.152 2020/04/08 03:01:28 msaitoh Exp $ */ +/* $NetBSD: miidevs_data.h,v 1.153 2020/06/23 14:35:59 msaitoh Exp $ */ /* * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * NetBSD: miidevs,v 1.167 2020/04/08 03:01:05 msaitoh Exp + * NetBSD: miidevs,v 1.168 2020/06/23 14:35:36 msaitoh Exp */ /*- @@ -258,7 +258,17 @@ struct mii_knowndev mii_knowndevs[] = { { MII_OUI_xxVIA, MII_MODEL_xxVIA_VT6103_2, MII_STR_xxVIA_VT6103_2 }, { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8601, MII_STR_xxVITESSE_VSC8601 }, { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8641, MII_STR_xxVITESSE_VSC8641 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8504, MII_STR_xxVITESSE_VSC8504 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8552, MII_STR_xxVITESSE_VSC8552 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8502, MII_STR_xxVITESSE_VSC8502 }, { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8501, MII_STR_xxVITESSE_VSC8501 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8531, MII_STR_xxVITESSE_VSC8531 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8662, MII_STR_xxVITESSE_VSC8662 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8514, MII_STR_xxVITESSE_VSC8514 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8512, MII_STR_xxVITESSE_VSC8512 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8522, MII_STR_xxVITESSE_VSC8522 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8658, MII_STR_xxVITESSE_VSC8658 }, + { MII_OUI_xxVITESSE, MII_MODEL_xxVITESSE_VSC8541, MII_STR_xxVITESSE_VSC8541 }, { MII_OUI_xxXAQTI, MII_MODEL_xxXAQTI_XMACII, MII_STR_xxXAQTI_XMACII }, { 0, 0, NULL } };