Module Name: src
Committed By: jdolecek
Date: Sat Jun 27 16:29:11 UTC 2020
Modified Files:
src/sys/dev/microcode/aic7xxx: aic79xx_reg.h aic7xxx_reg.h
aic7xxx_seq.h
Log Message:
regen - NFCI, confirmed by comparing compiled binary object before and
after
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/dev/microcode/aic7xxx/aic79xx_reg.h \
src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/microcode/aic7xxx/aic79xx_reg.h
diff -u src/sys/dev/microcode/aic7xxx/aic79xx_reg.h:1.11 src/sys/dev/microcode/aic7xxx/aic79xx_reg.h:1.12
--- src/sys/dev/microcode/aic7xxx/aic79xx_reg.h:1.11 Fri Aug 29 03:54:07 2003
+++ src/sys/dev/microcode/aic7xxx/aic79xx_reg.h Sat Jun 27 16:29:11 2020
@@ -160,13 +160,6 @@ ahd_reg_print_t ahd_dfstatus_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_arbctl_print;
-#else
-#define ahd_arbctl_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_sg_cache_shadow_print;
#else
#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
@@ -181,10 +174,10 @@ ahd_reg_print_t ahd_sg_cache_pre_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_typeptr_print;
+ahd_reg_print_t ahd_arbctl_print;
#else
-#define ahd_typeptr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
+#define ahd_arbctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -195,6 +188,13 @@ ahd_reg_print_t ahd_lqin_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_typeptr_print;
+#else
+#define ahd_typeptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_tagptr_print;
#else
#define ahd_tagptr_print(regvalue, cur_col, wrap) \
@@ -405,13 +405,6 @@ ahd_reg_print_t ahd_scsiseq1_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dlcount_print;
-#else
-#define ahd_dlcount_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_businitid_print;
#else
#define ahd_businitid_print(regvalue, cur_col, wrap) \
@@ -426,17 +419,17 @@ ahd_reg_print_t ahd_sxfrctl0_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sxfrctl1_print;
+ahd_reg_print_t ahd_dlcount_print;
#else
-#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
+#define ahd_dlcount_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sxfrctl2_print;
+ahd_reg_print_t ahd_sxfrctl1_print;
#else
-#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
+#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -447,17 +440,17 @@ ahd_reg_print_t ahd_bustargid_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dffstat_print;
+ahd_reg_print_t ahd_sxfrctl2_print;
#else
-#define ahd_dffstat_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
+#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_multargid_print;
+ahd_reg_print_t ahd_dffstat_print;
#else
-#define ahd_multargid_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
+#define ahd_dffstat_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -468,6 +461,13 @@ ahd_reg_print_t ahd_scsisigo_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_multargid_print;
+#else
+#define ahd_multargid_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_scsisigi_print;
#else
#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
@@ -517,17 +517,17 @@ ahd_reg_print_t ahd_selid_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sblkctl_print;
+ahd_reg_print_t ahd_optionmode_print;
#else
-#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
+#define ahd_optionmode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_optionmode_print;
+ahd_reg_print_t ahd_sblkctl_print;
#else
-#define ahd_optionmode_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
+#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -587,17 +587,17 @@ ahd_reg_print_t ahd_simode2_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lqistate_print;
+ahd_reg_print_t ahd_perrdiag_print;
#else
-#define ahd_lqistate_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
+#define ahd_perrdiag_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_perrdiag_print;
+ahd_reg_print_t ahd_lqistate_print;
#else
-#define ahd_perrdiag_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
+#define ahd_lqistate_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -685,6 +685,13 @@ ahd_reg_print_t ahd_simode3_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_lqomode0_print;
+#else
+#define ahd_lqomode0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_lqostat0_print;
#else
#define ahd_lqostat0_print(regvalue, cur_col, wrap) \
@@ -699,10 +706,10 @@ ahd_reg_print_t ahd_clrlqoint0_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lqomode0_print;
+ahd_reg_print_t ahd_lqomode1_print;
#else
-#define ahd_lqomode0_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
+#define ahd_lqomode1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -720,13 +727,6 @@ ahd_reg_print_t ahd_clrlqoint1_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lqomode1_print;
-#else
-#define ahd_lqomode1_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_os_space_cnt_print;
#else
#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \
@@ -755,10 +755,10 @@ ahd_reg_print_t ahd_gsfifo_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lqoscsctl_print;
+ahd_reg_print_t ahd_dffsxfrctl_print;
#else
-#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
+#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -769,10 +769,10 @@ ahd_reg_print_t ahd_nextscb_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dffsxfrctl_print;
+ahd_reg_print_t ahd_lqoscsctl_print;
#else
-#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
+#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -790,17 +790,17 @@ ahd_reg_print_t ahd_clrseqintsrc_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_seqimode_print;
+ahd_reg_print_t ahd_currscb_print;
#else
-#define ahd_seqimode_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
+#define ahd_currscb_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_currscb_print;
+ahd_reg_print_t ahd_seqimode_print;
#else
-#define ahd_currscb_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
+#define ahd_seqimode_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -979,17 +979,17 @@ ahd_reg_print_t ahd_seloid_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_pll400ctl0_print;
+ahd_reg_print_t ahd_fairness_print;
#else
-#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
+#define ahd_fairness_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_fairness_print;
+ahd_reg_print_t ahd_pll400ctl0_print;
#else
-#define ahd_fairness_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
+#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1070,17 +1070,17 @@ ahd_reg_print_t ahd_sghaddr_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sghcnt_print;
+ahd_reg_print_t ahd_scbhcnt_print;
#else
-#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
+#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbhcnt_print;
+ahd_reg_print_t ahd_sghcnt_print;
#else
-#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
+#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1119,13 +1119,6 @@ ahd_reg_print_t ahd_dchrxmsg0_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_roenable_print;
-#else
-#define ahd_roenable_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_ovlyrxmsg0_print;
#else
#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
@@ -1140,10 +1133,10 @@ ahd_reg_print_t ahd_cmcrxmsg0_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_nsenable_print;
+ahd_reg_print_t ahd_roenable_print;
#else
-#define ahd_nsenable_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
+#define ahd_roenable_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1168,6 +1161,13 @@ ahd_reg_print_t ahd_cmcrxmsg1_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_nsenable_print;
+#else
+#define ahd_nsenable_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_dchrxmsg2_print;
#else
#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
@@ -1203,6 +1203,13 @@ ahd_reg_print_t ahd_dchrxmsg3_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ovlyrxmsg3_print;
+#else
+#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_cmcrxmsg3_print;
#else
#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
@@ -1217,13 +1224,6 @@ ahd_reg_print_t ahd_pcixctl_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ovlyrxmsg3_print;
-#else
-#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_ovlyseqbcnt_print;
#else
#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
@@ -1245,13 +1245,6 @@ ahd_reg_print_t ahd_dchseqbcnt_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ovlyspltstat0_print;
-#else
-#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_cmcspltstat0_print;
#else
#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
@@ -1266,17 +1259,17 @@ ahd_reg_print_t ahd_dchspltstat0_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ovlyspltstat1_print;
+ahd_reg_print_t ahd_ovlyspltstat0_print;
#else
-#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_dchspltstat1_print;
+ahd_reg_print_t ahd_ovlyspltstat1_print;
#else
-#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1287,6 +1280,13 @@ ahd_reg_print_t ahd_cmcspltstat1_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_dchspltstat1_print;
+#else
+#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_sgrxmsg0_print;
#else
#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
@@ -1301,13 +1301,6 @@ ahd_reg_print_t ahd_slvspltoutadr0_print
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_slvspltoutadr1_print;
-#else
-#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_sgrxmsg1_print;
#else
#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
@@ -1315,10 +1308,10 @@ ahd_reg_print_t ahd_sgrxmsg1_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_slvspltoutadr2_print;
+ahd_reg_print_t ahd_slvspltoutadr1_print;
#else
-#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
+#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1329,6 +1322,13 @@ ahd_reg_print_t ahd_sgrxmsg2_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_slvspltoutadr2_print;
+#else
+#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_slvspltoutadr3_print;
#else
#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
@@ -1364,17 +1364,17 @@ ahd_reg_print_t ahd_slvspltoutattr1_prin
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_sgspltstat0_print;
+ahd_reg_print_t ahd_slvspltoutattr2_print;
#else
-#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
+#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_slvspltoutattr2_print;
+ahd_reg_print_t ahd_sgspltstat0_print;
#else
-#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
+#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1462,13 +1462,6 @@ ahd_reg_print_t ahd_sg_state_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_data_count_odd_print;
-#else
-#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_targpcistat_print;
#else
#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
@@ -1476,17 +1469,17 @@ ahd_reg_print_t ahd_targpcistat_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbptr_print;
+ahd_reg_print_t ahd_data_count_odd_print;
#else
-#define ahd_scbptr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
+#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_scbautoptr_print;
+ahd_reg_print_t ahd_scbptr_print;
#else
-#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
+#define ahd_scbptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1497,10 +1490,10 @@ ahd_reg_print_t ahd_ccscbacnt_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ccscbaddr_print;
+ahd_reg_print_t ahd_scbautoptr_print;
#else
-#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
+#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1518,6 +1511,13 @@ ahd_reg_print_t ahd_ccsgaddr_print;
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ccscbaddr_print;
+#else
+#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_ccscbctl_print;
#else
#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
@@ -1903,17 +1903,17 @@ ahd_reg_print_t ahd_curaddr_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_lastaddr_print;
+ahd_reg_print_t ahd_intvec2_addr_print;
#else
-#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
+#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_intvec2_addr_print;
+ahd_reg_print_t ahd_lastaddr_print;
#else
-#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
+#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1931,13 +1931,6 @@ ahd_reg_print_t ahd_accum_save_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahd_reg_print_t ahd_ahd_pci_config_base_print;
-#else
-#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \
- ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap)
-#endif
-
-#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_sram_base_print;
#else
#define ahd_sram_base_print(regvalue, cur_col, wrap) \
@@ -1952,6 +1945,13 @@ ahd_reg_print_t ahd_waiting_scb_tails_pr
#endif
#if AIC_DEBUG_REGISTERS
+ahd_reg_print_t ahd_ahd_pci_config_base_print;
+#else
+#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \
+ ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap)
+#endif
+
+#if AIC_DEBUG_REGISTERS
ahd_reg_print_t ahd_waiting_tid_head_print;
#else
#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \
@@ -2510,11 +2510,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define FIFOFULL 0x02
#define FIFOEMP 0x01
-#define ARBCTL 0x1b
-#define RESET_HARB 0x80
-#define RETRY_SWEN 0x08
-#define USE_TIME 0x07
-
#define SG_CACHE_SHADOW 0x1b
#define ODD_SEG 0x04
#define LAST_SEG 0x02
@@ -2522,10 +2517,15 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SG_CACHE_PRE 0x1b
-#define TYPEPTR 0x20
+#define ARBCTL 0x1b
+#define RESET_HARB 0x80
+#define RETRY_SWEN 0x08
+#define USE_TIME 0x07
#define LQIN 0x20
+#define TYPEPTR 0x20
+
#define TAGPTR 0x21
#define LUNPTR 0x22
@@ -2617,8 +2617,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SCSISEQ1 0x3b
-#define DLCOUNT 0x3c
-
#define BUSINITID 0x3c
#define SXFRCTL0 0x3c
@@ -2627,6 +2625,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define BIOSCANCELEN 0x10
#define SPIOEN 0x08
+#define DLCOUNT 0x3c
+
#define SXFRCTL1 0x3d
#define BITBUCKET 0x80
#define ENSACHK 0x40
@@ -2636,13 +2636,13 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define ACTNEGEN 0x02
#define STPWEN 0x01
+#define BUSTARGID 0x3e
+
#define SXFRCTL2 0x3e
#define AUTORSTDIS 0x10
#define CMDDMAEN 0x08
#define ASU 0x07
-#define BUSTARGID 0x3e
-
#define DFFSTAT 0x3f
#define CURRFIFO 0x03
#define FIFO1FREE 0x20
@@ -2651,8 +2651,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CURRFIFO_1 0x01
#define CURRFIFO_0 0x00
-#define MULTARGID 0x40
-
#define SCSISIGO 0x40
#define CDO 0x80
#define IOO 0x40
@@ -2663,6 +2661,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define REQO 0x02
#define ACKO 0x01
+#define MULTARGID 0x40
+
#define SCSISIGI 0x41
#define ATNI 0x10
#define SELI 0x08
@@ -2693,13 +2693,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SELID_MASK 0xf0
#define ONEBIT 0x08
-#define SBLKCTL 0x4a
-#define DIAGLEDEN 0x80
-#define DIAGLEDON 0x40
-#define ENAB40 0x08
-#define ENAB20 0x04
-#define SELWIDE 0x02
-
#define OPTIONMODE 0x4a
#define OPTIONMODE_DEFAULTS 0x02
#define BIOSCANCTL 0x80
@@ -2709,6 +2702,13 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define ENDGFORMCHK 0x04
#define AUTO_MSGOUT_DE 0x02
+#define SBLKCTL 0x4a
+#define DIAGLEDEN 0x80
+#define DIAGLEDON 0x40
+#define ENAB40 0x08
+#define ENAB20 0x04
+#define SELWIDE 0x02
+
#define SIMODE0 0x4b
#define ENSELDO 0x40
#define ENSELDI 0x20
@@ -2779,8 +2779,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define ENSDONE 0x02
#define ENDMADONE 0x01
-#define LQISTATE 0x4e
-
#define PERRDIAG 0x4e
#define HIZERO 0x80
#define HIPERR 0x40
@@ -2791,6 +2789,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define DGFORMERR 0x02
#define DTERR 0x01
+#define LQISTATE 0x4e
+
#define SOFFCNT 0x4f
#define LQOSTATE 0x4f
@@ -2871,6 +2871,13 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define ENNTRAMPERR 0x02
#define ENOSRAMPERR 0x01
+#define LQOMODE0 0x54
+#define ENLQOTARGSCBPERR 0x10
+#define ENLQOSTOPT2 0x08
+#define ENLQOATNLQ 0x04
+#define ENLQOATNPKT 0x02
+#define ENLQOTCRC 0x01
+
#define LQOSTAT0 0x54
#define LQOTARGSCBPERR 0x10
#define LQOSTOPT2 0x08
@@ -2885,12 +2892,12 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CLRLQOATNPKT 0x02
#define CLRLQOTCRC 0x01
-#define LQOMODE0 0x54
-#define ENLQOTARGSCBPERR 0x10
-#define ENLQOSTOPT2 0x08
-#define ENLQOATNLQ 0x04
-#define ENLQOATNPKT 0x02
-#define ENLQOTCRC 0x01
+#define LQOMODE1 0x55
+#define ENLQOINITSCBPERR 0x10
+#define ENLQOSTOPI2 0x08
+#define ENLQOBADQAS 0x04
+#define ENLQOBUSFREE 0x02
+#define ENLQOPHACHGINPKT 0x01
#define LQOSTAT1 0x55
#define LQOINITSCBPERR 0x10
@@ -2906,13 +2913,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CLRLQOBUSFREE 0x02
#define CLRLQOPHACHGINPKT 0x01
-#define LQOMODE1 0x55
-#define ENLQOINITSCBPERR 0x10
-#define ENLQOSTOPI2 0x08
-#define ENLQOBADQAS 0x04
-#define ENLQOBUSFREE 0x02
-#define ENLQOPHACHGINPKT 0x01
-
#define OS_SPACE_CNT 0x56
#define LQOSTAT2 0x56
@@ -2933,18 +2933,18 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define GSFIFO 0x58
-#define LQOSCSCTL 0x5a
-#define LQOH2A_VERSION 0x80
-#define LQONOCHKOVER 0x01
-
-#define NEXTSCB 0x5a
-
#define DFFSXFRCTL 0x5a
#define DFFBITBUCKET 0x08
#define CLRSHCNT 0x04
#define CLRCHN 0x02
#define RSTCHN 0x01
+#define NEXTSCB 0x5a
+
+#define LQOSCSCTL 0x5a
+#define LQOH2A_VERSION 0x80
+#define LQONOCHKOVER 0x01
+
#define SEQINTSRC 0x5b
#define CTXTDONE 0x40
#define SAVEPTRS 0x20
@@ -2963,6 +2963,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CLRCFG4ICMD 0x02
#define CLRCFG4TCMD 0x01
+#define CURRSCB 0x5c
+
#define SEQIMODE 0x5c
#define ENCTXTDONE 0x40
#define ENSAVEPTRS 0x20
@@ -2972,8 +2974,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define ENCFG4ICMD 0x02
#define ENCFG4TCMD 0x01
-#define CURRSCB 0x5c
-
#define MDFFSTAT 0x5d
#define SHCNTNEGATIVE 0x40
#define SHCNTMINUS1 0x20
@@ -3055,6 +3055,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SELOID 0x6b
+#define FAIRNESS 0x6c
+
#define PLL400CTL0 0x6c
#define PLL_VCOSEL 0x80
#define PLL_PWDN 0x40
@@ -3064,8 +3066,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define PLL_DLPF 0x02
#define PLL_ENFBM 0x01
-#define FAIRNESS 0x6c
-
#define PLL400CTL1 0x6d
#define PLL_CNTEN 0x80
#define PLL_CNTCLR 0x40
@@ -3092,10 +3092,10 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SGHADDR 0x7c
-#define SGHCNT 0x84
-
#define SCBHCNT 0x84
+#define SGHCNT 0x84
+
#define DFF_THRSH 0x88
#define WR_DFTHRSH 0x70
#define RD_DFTHRSH 0x07
@@ -3128,6 +3128,10 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define DCHRXMSG0 0x90
+#define OVLYRXMSG0 0x90
+
+#define CMCRXMSG0 0x90
+
#define ROENABLE 0x90
#define MSIROEN 0x20
#define OVLYROEN 0x10
@@ -3136,9 +3140,11 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define DCH1ROEN 0x02
#define DCH0ROEN 0x01
-#define OVLYRXMSG0 0x90
+#define DCHRXMSG1 0x91
-#define CMCRXMSG0 0x90
+#define OVLYRXMSG1 0x91
+
+#define CMCRXMSG1 0x91
#define NSENABLE 0x91
#define MSINSEN 0x20
@@ -3148,12 +3154,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define DCH1NSEN 0x02
#define DCH0NSEN 0x01
-#define DCHRXMSG1 0x91
-
-#define OVLYRXMSG1 0x91
-
-#define CMCRXMSG1 0x91
-
#define DCHRXMSG2 0x92
#define OVLYRXMSG2 0x92
@@ -3164,6 +3164,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define DCHRXMSG3 0x93
+#define OVLYRXMSG3 0x93
+
#define CMCRXMSG3 0x93
#define PCIXCTL 0x93
@@ -3175,26 +3177,24 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define TSCSERREN 0x02
#define CMPABCDIS 0x01
-#define OVLYRXMSG3 0x93
-
#define OVLYSEQBCNT 0x94
#define CMCSEQBCNT 0x94
#define DCHSEQBCNT 0x94
-#define OVLYSPLTSTAT0 0x96
-
#define CMCSPLTSTAT0 0x96
#define DCHSPLTSTAT0 0x96
-#define OVLYSPLTSTAT1 0x97
+#define OVLYSPLTSTAT0 0x96
-#define DCHSPLTSTAT1 0x97
+#define OVLYSPLTSTAT1 0x97
#define CMCSPLTSTAT1 0x97
+#define DCHSPLTSTAT1 0x97
+
#define SGRXMSG0 0x98
#define CDNUM 0xf8
#define CFNUM 0x07
@@ -3202,19 +3202,19 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SLVSPLTOUTADR0 0x98
#define LOWER_ADDR 0x7f
+#define SGRXMSG1 0x99
+#define CBNUM 0xff
+
#define SLVSPLTOUTADR1 0x99
#define REQ_DNUM 0xf8
#define REQ_FNUM 0x07
-#define SGRXMSG1 0x99
-#define CBNUM 0xff
+#define SGRXMSG2 0x9a
+#define MINDEX 0xff
#define SLVSPLTOUTADR2 0x9a
#define REQ_BNUM 0xff
-#define SGRXMSG2 0x9a
-#define MINDEX 0xff
-
#define SLVSPLTOUTADR3 0x9b
#define TAG_NUM 0x1f
#define RLXORD 0x10
@@ -3231,6 +3231,9 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CMPLT_DNUM 0xf8
#define CMPLT_FNUM 0x07
+#define SLVSPLTOUTATTR2 0x9e
+#define CMPLT_BNUM 0xff
+
#define SGSPLTSTAT0 0x9e
#define STAETERM 0x80
#define SCBCERR 0x40
@@ -3241,9 +3244,6 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define RXSCEMSG 0x02
#define RXSPLTRSP 0x01
-#define SLVSPLTOUTATTR2 0x9e
-#define CMPLT_BNUM 0xff
-
#define SGSPLTSTAT1 0x9f
#define RXDATABUCKET 0x01
@@ -3280,29 +3280,29 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define LOADING_NEEDED 0x02
#define SEGS_AVAIL 0x01
-#define DATA_COUNT_ODD 0xa7
-
#define TARGPCISTAT 0xa7
#define DPE 0x80
#define SSE 0x40
#define STA 0x08
#define TWATERR 0x02
+#define DATA_COUNT_ODD 0xa7
+
#define SCBPTR 0xa8
+#define CCSCBACNT 0xab
+
#define SCBAUTOPTR 0xab
#define AUSCBPTR_EN 0x80
#define SCBPTR_ADDR 0x38
#define SCBPTR_OFF 0x07
-#define CCSCBACNT 0xab
-
-#define CCSCBADDR 0xac
-
#define CCSCBADR_BK 0xac
#define CCSGADDR 0xac
+#define CCSCBADDR 0xac
+
#define CCSCBCTL 0xad
#define CCSCBDONE 0x80
#define ARRDONE 0x40
@@ -3498,20 +3498,20 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define CURADDR 0xf4
-#define LASTADDR 0xf6
-
#define INTVEC2_ADDR 0xf6
+#define LASTADDR 0xf6
+
#define LONGJMP_ADDR 0xf8
#define ACCUM_SAVE 0xfa
-#define AHD_PCI_CONFIG_BASE 0x100
-
#define SRAM_BASE 0x100
#define WAITING_SCB_TAILS 0x100
+#define AHD_PCI_CONFIG_BASE 0x100
+
#define WAITING_TID_HEAD 0x120
#define WAITING_TID_TAIL 0x122
@@ -3534,8 +3534,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define PRELOADEN 0x80
#define WIDEODD 0x40
#define SCSIEN 0x20
-#define SDMAENACK 0x10
#define SDMAEN 0x10
+#define SDMAENACK 0x10
#define HDMAEN 0x08
#define HDMAENACK 0x08
#define DIRECTION 0x04
@@ -3701,6 +3701,26 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define SCB_DISCONNECTED_LISTS 0x1b8
+#define AHD_TIMER_MAX_US 0x18ffe7
+#define STIMESEL_MIN 0x18
+#define TARGET_CMD_CMPLT 0xfe
+#define SEEOP_ERAL_ADDR 0x80
+#define SRC_MODE_SHIFT 0x00
+#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
+#define MAX_OFFSET_PACED 0xfe
+#define SEEOP_EWDS_ADDR 0x00
+#define AHD_ANNEXCOL_AMPLITUDE 0x06
+#define AHD_PRECOMP_CUTBACK_29 0x06
+#define AHD_ANNEXCOL_PER_DEV0 0x04
+#define AHD_TIMER_MAX_TICKS 0xffff
+#define STATUS_PKT_SENSE 0xff
+#define CMD_GROUP_CODE_SHIFT 0x05
+#define BUS_8_BIT 0x00
+#define CCSGRAM_MAXSEGS 0x10
+#define AHD_AMPLITUDE_DEF 0x07
+#define AHD_SLEWRATE_DEF_REVB 0x08
+#define AHD_PRECOMP_CUTBACK_37 0x07
+#define AHD_PRECOMP_SHIFT 0x00
#define PKT_OVERRUN_BUFSIZE 0x200
#define SCB_TRANSFER_SIZE_FULL_LUN 0x38
#define TARGET_DATA_IN 0x01
@@ -3722,17 +3742,8 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define AHD_AMPLITUDE_MASK 0x07
#define LUNLEN_SINGLE_LEVEL_LUN 0x0f
#define DST_MODE_SHIFT 0x04
-#define AHD_TIMER_MAX_TICKS 0xffff
-#define STATUS_PKT_SENSE 0xff
-#define CMD_GROUP_CODE_SHIFT 0x05
-#define BUS_8_BIT 0x00
#define STIMESEL_SHIFT 0x03
-#define CCSGRAM_MAXSEGS 0x10
#define SEEOP_WRAL_ADDR 0x40
-#define AHD_AMPLITUDE_DEF 0x07
-#define AHD_SLEWRATE_DEF_REVB 0x08
-#define AHD_PRECOMP_CUTBACK_37 0x07
-#define AHD_PRECOMP_SHIFT 0x00
#define AHD_ANNEXCOL_PRECOMP_SLEW 0x04
#define STATUS_QUEUE_FULL 0x28
#define MAX_OFFSET_NON_PACED 0x7f
@@ -3740,34 +3751,23 @@ ahd_reg_print_t ahd_scb_disconnected_lis
#define NUMDSPS 0x14
#define AHD_NUM_PER_DEV_ANNEXCOLS 0x04
#define NVRAM_SCB_OFFSET 0x2c
-#define AHD_TIMER_MAX_US 0x18ffe7
#define AHD_SENSE_BUFSIZE 0x100
#define STIMESEL_BUG_ADJ 0x08
-#define STIMESEL_MIN 0x18
#define INVALID_ADDR 0x80
-#define TARGET_CMD_CMPLT 0xfe
-#define SEEOP_ERAL_ADDR 0x80
-#define SRC_MODE_SHIFT 0x00
-#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
-#define MAX_OFFSET_PACED 0xfe
#define CCSGADDR_MAX 0x80
#define MK_MESSAGE_BIT_OFFSET 0x04
-#define SEEOP_EWDS_ADDR 0x00
-#define AHD_ANNEXCOL_AMPLITUDE 0x06
#define AHD_SLEWRATE_SHIFT 0x03
-#define AHD_PRECOMP_CUTBACK_29 0x06
-#define AHD_ANNEXCOL_PER_DEV0 0x04
#define B_CURRFIFO_0 0x02
/* Downloaded Constant Definitions */
+#define SG_SIZEOF 0x04
+#define SG_PREFETCH_ADDR_MASK 0x03
+#define SG_PREFETCH_ALIGN_MASK 0x02
#define SCB_TRANSFER_SIZE 0x06
#define SG_PREFETCH_CNT 0x00
#define SG_PREFETCH_CNT_LIMIT 0x01
-#define SG_PREFETCH_ADDR_MASK 0x03
-#define SG_PREFETCH_ALIGN_MASK 0x02
#define PKT_OVERRUN_BUFOFFSET 0x05
-#define SG_SIZEOF 0x04
#define DOWNLOAD_CONST_COUNT 0x07
Index: src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h
diff -u src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h:1.11 src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h:1.12
--- src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h:1.11 Thu Nov 16 01:33:06 2006
+++ src/sys/dev/microcode/aic7xxx/aic7xxx_seq.h Sat Jun 27 16:29:11 2020
@@ -2,8 +2,8 @@
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
- * $NetBSD: aic7xxx_seq.h,v 1.11 2006/11/16 01:33:06 christos Exp $
- * $NetBSD: aic7xxx_seq.h,v 1.11 2006/11/16 01:33:06 christos Exp $
+ * $NetBSD: aic7xxx_seq.h,v 1.12 2020/06/27 16:29:11 jdolecek Exp $
+ * $NetBSD: aic7xxx_seq.h,v 1.12 2020/06/27 16:29:11 jdolecek Exp $
*/
static uint8_t seqprog[] = {
0xb2, 0x00, 0x00, 0x08,
Index: src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h
diff -u src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h:1.2 src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h:1.3
--- src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h:1.2 Sat Apr 19 19:27:50 2003
+++ src/sys/dev/microcode/aic7xxx/aic7xxx_reg.h Sat Jun 27 16:29:11 2020
@@ -2,8 +2,8 @@
* DO NOT EDIT - This file is automatically generated
* from the following source files:
*
- * $NetBSD: aic7xxx_reg.h,v 1.2 2003/04/19 19:27:50 fvdl Exp $
- * $NetBSD: aic7xxx_reg.h,v 1.2 2003/04/19 19:27:50 fvdl Exp $
+ * $NetBSD: aic7xxx_reg.h,v 1.3 2020/06/27 16:29:11 jdolecek Exp $
+ * $NetBSD: aic7xxx_reg.h,v 1.3 2020/06/27 16:29:11 jdolecek Exp $
*/
typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
typedef struct ahc_reg_parse_entry {
@@ -34,17 +34,17 @@ ahc_reg_print_t ahc_sxfrctl1_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_scsisigo_print;
+ahc_reg_print_t ahc_scsisigi_print;
#else
-#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
+#define ahc_scsisigi_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_scsisigi_print;
+ahc_reg_print_t ahc_scsisigo_print;
#else
-#define ahc_scsisigi_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
+#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -76,17 +76,17 @@ ahc_reg_print_t ahc_scsidath_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_stcnt_print;
+ahc_reg_print_t ahc_optionmode_print;
#else
-#define ahc_stcnt_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
+#define ahc_optionmode_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_optionmode_print;
+ahc_reg_print_t ahc_stcnt_print;
#else
-#define ahc_optionmode_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
+#define ahc_stcnt_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -601,17 +601,17 @@ ahc_reg_print_t ahc_sram_base_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_bctl_print;
+ahc_reg_print_t ahc_dscommand0_print;
#else
-#define ahc_bctl_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
+#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_dscommand0_print;
+ahc_reg_print_t ahc_bctl_print;
#else
-#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
+#define ahc_bctl_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -636,17 +636,17 @@ ahc_reg_print_t ahc_busspd_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_dspcistatus_print;
+ahc_reg_print_t ahc_hs_mailbox_print;
#else
-#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
+#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_hs_mailbox_print;
+ahc_reg_print_t ahc_dspcistatus_print;
#else
-#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
+#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -769,17 +769,17 @@ ahc_reg_print_t ahc_qoutfifo_print;
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_scsiphase_print;
+ahc_reg_print_t ahc_qoutcnt_print;
#else
-#define ahc_scsiphase_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
+#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
-ahc_reg_print_t ahc_qoutcnt_print;
+ahc_reg_print_t ahc_scsiphase_print;
#else
-#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
- ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
+#define ahc_scsiphase_print(regvalue, cur_col, wrap) \
+ ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
#endif
#if AIC_DEBUG_REGISTERS
@@ -1091,6 +1091,15 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define ACTNEGEN 0x02
#define STPWEN 0x01
+#define SCSISIGI 0x03
+#define P_DATAIN_DT 0x60
+#define P_DATAOUT_DT 0x20
+#define ATNI 0x10
+#define SELI 0x08
+#define BSYI 0x04
+#define REQI 0x02
+#define ACKI 0x01
+
#define SCSISIGO 0x03
#define CDO 0x80
#define IOO 0x40
@@ -1101,15 +1110,6 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define REQO 0x02
#define ACKO 0x01
-#define SCSISIGI 0x03
-#define P_DATAIN_DT 0x60
-#define P_DATAOUT_DT 0x20
-#define ATNI 0x10
-#define SELI 0x08
-#define BSYI 0x04
-#define REQI 0x02
-#define ACKI 0x01
-
#define SCSIRATE 0x04
#define SXFR 0x70
#define SXFR_ULTRA2 0x0f
@@ -1126,8 +1126,6 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define SCSIDATH 0x07
-#define STCNT 0x08
-
#define OPTIONMODE 0x08
#define OPTIONMODE_DEFAULTS 0x03
#define AUTORATEEN 0x80
@@ -1139,14 +1137,16 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define AUTO_MSGOUT_DE 0x02
#define DIS_MSGIN_DUALEDGE 0x01
+#define STCNT 0x08
+
#define TARGCRCCNT 0x0a
#define CLRSINT0 0x0b
#define CLRSELDO 0x40
#define CLRSELDI 0x20
#define CLRSELINGO 0x10
-#define CLRSWRAP 0x08
#define CLRIOERR 0x08
+#define CLRSWRAP 0x08
#define CLRSPIORDY 0x02
#define SSTAT0 0x0b
@@ -1265,8 +1265,8 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define BRDDAT5 0x20
#define BRDDAT4 0x10
#define BRDSTB 0x10
-#define BRDCS 0x08
#define BRDDAT3 0x08
+#define BRDCS 0x08
#define BRDDAT2 0x04
#define BRDRW 0x04
#define BRDCTL1 0x02
@@ -1469,10 +1469,6 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define SRAM_BASE 0x70
-#define BCTL 0x84
-#define ACE 0x08
-#define ENABLE 0x01
-
#define DSCOMMAND0 0x84
#define CACHETHEN 0x80
#define DPARCKEN 0x40
@@ -1483,6 +1479,10 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define USCBSIZE32 0x02
#define CIOPARCKEN 0x01
+#define BCTL 0x84
+#define ACE 0x08
+#define ENABLE 0x01
+
#define BUSTIME 0x85
#define BOFF 0xf0
#define BON 0x0f
@@ -1498,14 +1498,14 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define STBOFF 0x38
#define STBON 0x07
-#define DSPCISTATUS 0x86
-#define DFTHRSH_100 0xc0
-
#define HS_MAILBOX 0x86
#define HOST_MAILBOX 0xf0
#define HOST_TQINPOS 0x80
#define SEQ_MAILBOX 0x0f
+#define DSPCISTATUS 0x86
+#define DFTHRSH_100 0xc0
+
#define HCNTRL 0x87
#define POWRDN 0x40
#define SWINT 0x10
@@ -1597,6 +1597,8 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define QOUTFIFO 0x9d
+#define QOUTCNT 0x9e
+
#define SCSIPHASE 0x9e
#define DATA_PHASE_MASK 0x03
#define STATUS_PHASE 0x20
@@ -1606,16 +1608,14 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define DATA_IN_PHASE 0x02
#define DATA_OUT_PHASE 0x01
-#define QOUTCNT 0x9e
-
#define SFUNCT 0x9f
#define ALT_MODE 0x80
#define SCB_BASE 0xa0
#define SCB_CDB_PTR 0xa0
-#define SCB_CDB_STORE 0xa0
#define SCB_RESIDUAL_DATACNT 0xa0
+#define SCB_CDB_STORE 0xa0
#define SCB_RESIDUAL_SGPTR 0xa4
@@ -1640,8 +1640,8 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define SCB_CONTROL 0xb8
#define SCB_TAG_TYPE 0x03
-#define TARGET_SCB 0x80
#define STATUS_RCVD 0x80
+#define TARGET_SCB 0x80
#define DISCENB 0x40
#define TAG_ENB 0x20
#define MK_MESSAGE 0x10
@@ -1744,8 +1744,8 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define RD_DFTHRSH_63 0x03
#define RD_DFTHRSH_50 0x02
#define RD_DFTHRSH_25 0x01
-#define WR_DFTHRSH_MIN 0x00
#define RD_DFTHRSH_MIN 0x00
+#define WR_DFTHRSH_MIN 0x00
#define SG_CACHE_SHADOW 0xfc
#define SG_ADDR_MASK 0xf8
@@ -1756,12 +1756,6 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define SG_CACHE_PRE 0xfc
-#define TARGET_DATA_IN 0x01
-#define STATUS_BUSY 0x08
-#define BUS_16_BIT 0x01
-#define TID_SHIFT 0x04
-#define SCB_UPLOAD_SIZE 0x20
-#define HOST_MAILBOX_SHIFT 0x04
#define MAX_OFFSET_ULTRA2 0x7f
#define SCB_LIST_NULL 0xff
#define HOST_MSG 0xff
@@ -1770,9 +1764,15 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
#define CMD_GROUP_CODE_SHIFT 0x05
#define BUS_8_BIT 0x00
#define CCSGRAM_MAXSEGS 0x10
+#define TARGET_DATA_IN 0x01
#define STATUS_QUEUE_FULL 0x28
+#define STATUS_BUSY 0x08
#define MAX_OFFSET_8BIT 0x0f
+#define BUS_16_BIT 0x01
+#define TID_SHIFT 0x04
#define SCB_DOWNLOAD_SIZE_64 0x30
+#define SCB_UPLOAD_SIZE 0x20
+#define HOST_MAILBOX_SHIFT 0x04
#define MAX_OFFSET_16BIT 0x08
#define TARGET_CMD_CMPLT 0xfe
#define SG_SIZEOF 0x08
@@ -1783,10 +1783,10 @@ ahc_reg_print_t ahc_sg_cache_pre_print;
/* Downloaded Constant Definitions */
-#define SG_PREFETCH_CNT 0x04
#define SG_PREFETCH_ADDR_MASK 0x06
#define SG_PREFETCH_ALIGN_MASK 0x05
#define QOUTFIFO_OFFSET 0x00
+#define SG_PREFETCH_CNT 0x04
#define INVERTED_CACHESIZE_MASK 0x03
#define CACHESIZE_MASK 0x02
#define QINFIFO_OFFSET 0x01
