Module Name: src
Committed By: ryo
Date: Sun Jul 19 07:32:43 UTC 2020
Modified Files:
src/sys/crypto/aes/arch/arm: aes_armv8_64.S
Log Message:
fix build with clang/llvm.
clang aarch64 assembler doesn't accept optional number of lanes of vector
register.
(but ARMARM says that an assembler must accept it)
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/crypto/aes/arch/arm/aes_armv8_64.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/crypto/aes/arch/arm/aes_armv8_64.S
diff -u src/sys/crypto/aes/arch/arm/aes_armv8_64.S:1.4 src/sys/crypto/aes/arch/arm/aes_armv8_64.S:1.5
--- src/sys/crypto/aes/arch/arm/aes_armv8_64.S:1.4 Tue Jun 30 23:06:02 2020
+++ src/sys/crypto/aes/arch/arm/aes_armv8_64.S Sun Jul 19 07:32:43 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: aes_armv8_64.S,v 1.4 2020/06/30 23:06:02 riastradh Exp $ */
+/* $NetBSD: aes_armv8_64.S,v 1.5 2020/07/19 07:32:43 ryo Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -238,8 +238,8 @@ ENTRY(aesarmv8_setenckey192)
*/
/* v1.4s := (nrk[0], nrk[1], nrk[1], nrk[1]) */
- dup v1.4s, v5.4s[3]
- mov v1.4s[0], v5.4s[2]
+ dup v1.4s, v5.s[3]
+ mov v1.s[0], v5.s[2]
/*
* v6.4s := (0, 0, rklo[0], rklo[1])
@@ -257,7 +257,7 @@ ENTRY(aesarmv8_setenckey192)
* and v5.4s = (rk[2], rk[3], xxx, xxx). Set
* v2.4s := (rk[0], rk[1], rk[2], rk[3])
*/
- mov v2.2d[1], v5.2d[0]
+ mov v2.d[1], v5.d[0]
/* store two round keys */
stp q2, q3, [x0], #0x20
@@ -325,7 +325,7 @@ ENTRY(aesarmv8_setenckey192)
ext v5.16b, v0.16b, v4.16b, #12
/* v2.4s := (nnrk[3], nnrk[3], xxx, xxx) */
- dup v2.4s, v1.4s[3]
+ dup v2.4s, v1.s[3]
/*
* v2.4s := (nnnrklo[0] = nnrk[3] ^ nrk[2],
