CVS commit: src/sys/arch/mips/cavium

[Jared D. McNeill]

Module Name:    src
Committed By:   jmcneill
Date:           Mon Jul 20 13:30:41 UTC 2020

Modified Files:
        src/sys/arch/mips/cavium: octeon_intr.c

Log Message:
Fix confusion between ipi bitmask and mbox register bit assignments.


To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/cavium/octeon_intr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/mips/cavium/octeon_intr.c
diff -u src/sys/arch/mips/cavium/octeon_intr.c:1.18 src/sys/arch/mips/cavium/octeon_intr.c:1.19
--- src/sys/arch/mips/cavium/octeon_intr.c:1.18	Fri Jul 17 21:59:30 2020
+++ src/sys/arch/mips/cavium/octeon_intr.c	Mon Jul 20 13:30:41 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $	*/
+/*	$NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -176,7 +176,7 @@ struct octeon_intrhand ipi_intrhands[2] 
 #define	OCTEON_IPI_SCHED(n)	__BIT((n) + 0)
 #define	OCTEON_IPI_HIGH(n)	__BIT((n) + 16)
 
-static uint64_t octeon_ipi_mask[NIPIS] = {
+static uint32_t octeon_ipi_mbox_mask[NIPIS] = {
 	[IPI_NOP]		= OCTEON_IPI_SCHED(IPI_NOP),
 	[IPI_AST]		= OCTEON_IPI_SCHED(IPI_AST),
 	[IPI_SHOOTDOWN]		= OCTEON_IPI_SCHED(IPI_SHOOTDOWN),
@@ -516,16 +516,21 @@ octeon_ipi_intr(void *arg)
 {
 	struct cpu_info * const ci = curcpu();
 	struct cpu_softc * const cpu = ci->ci_softc;
-	uint32_t ipi_mask = (uintptr_t) arg;
+	uint32_t mbox_mask = (uintptr_t) arg;
+	uint32_t ipi_mask;
 
-	KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
-	    "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
+	KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+	    "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
 
-	ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
-	if (ipi_mask == 0)
+	mbox_mask &= mips3_ld(cpu->cpu_mbox_set);
+	if (mbox_mask == 0)
 		return 0;
 
-	mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
+	mips3_sd(cpu->cpu_mbox_clr, mbox_mask);
+
+	ipi_mask = mbox_mask;
+	if (ci->ci_cpl >= IPL_SCHED)
+		ipi_mask >>= 16;
 
 	KASSERT(ipi_mask < __BIT(NIPIS));
 
@@ -573,11 +578,12 @@ octeon_send_ipi(struct cpu_info *ci, int
 		return -1;
 
 	struct cpu_softc * const cpu = ci->ci_softc;
-	const uint64_t ipi_mask = octeon_ipi_mask[req];
+	const uint32_t mbox_mask = octeon_ipi_mbox_mask[req];
+	const uint32_t ipi_mask = __BIT(req);
 
 	atomic_or_64(&ci->ci_request_ipis, ipi_mask);
 
-	mips3_sd(cpu->cpu_mbox_set, ipi_mask);
+	mips3_sd(cpu->cpu_mbox_set, mbox_mask);
 
 	return 0;
 }