Module Name:    src
Committed By:   mrg
Date:           Tue Feb  2 04:28:56 UTC 2010

Modified Files:
        src/sys/arch/sparc64/include: cpu.h pmap.h
        src/sys/arch/sparc64/sparc64: db_interface.c ipifuncs.c locore.s pmap.c

Log Message:
- split sp_tlb_flush_pte() and switchtoctx() into sp_tlb_flush_pte_us()/
  sp_tlb_flush_pte_usiii() and switchtoctx_us()/switchtoctx_usiii() and
  implement the latter while i'm here.  it works ... sometimes i think,
  but also sometimes panics/hangs.
- fix a comment in sparc64_ipi_flush_pte_usiii()


To generate a diff of this commit:
cvs rdiff -u -r1.87 -r1.88 src/sys/arch/sparc64/include/cpu.h
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/sparc64/include/pmap.h
cvs rdiff -u -r1.120 -r1.121 src/sys/arch/sparc64/sparc64/db_interface.c
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/sparc64/sparc64/ipifuncs.c
cvs rdiff -u -r1.309 -r1.310 src/sys/arch/sparc64/sparc64/locore.s
cvs rdiff -u -r1.248 -r1.249 src/sys/arch/sparc64/sparc64/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/sparc64/include/cpu.h
diff -u src/sys/arch/sparc64/include/cpu.h:1.87 src/sys/arch/sparc64/include/cpu.h:1.88
--- src/sys/arch/sparc64/include/cpu.h:1.87	Wed Oct 21 21:12:03 2009
+++ src/sys/arch/sparc64/include/cpu.h	Tue Feb  2 04:28:55 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.87 2009/10/21 21:12:03 rmind Exp $ */
+/*	$NetBSD: cpu.h,v 1.88 2010/02/02 04:28:55 mrg Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -339,7 +339,8 @@
 struct pcb;
 void	snapshot(struct pcb *);
 struct frame *getfp(void);
-void	switchtoctx(int);
+void	switchtoctx_us(int);
+void	switchtoctx_usiii(int);
 void	next_tick(long);
 /* trap.c */
 void	kill_user_windows(struct lwp *);

Index: src/sys/arch/sparc64/include/pmap.h
diff -u src/sys/arch/sparc64/include/pmap.h:1.46 src/sys/arch/sparc64/include/pmap.h:1.47
--- src/sys/arch/sparc64/include/pmap.h:1.46	Mon Feb  1 07:01:41 2010
+++ src/sys/arch/sparc64/include/pmap.h	Tue Feb  2 04:28:56 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.46 2010/02/01 07:01:41 mrg Exp $	*/
+/*	$NetBSD: pmap.h,v 1.47 2010/02/02 04:28:56 mrg Exp $	*/
 
 /*-
  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -206,8 +206,8 @@
 
 /* SPARC64 specific */
 /* Assembly routines to flush TLB mappings */
-void sp_tlb_flush_pte(vaddr_t, int);
-void sp_tlb_flush_ctx(int);
+void sp_tlb_flush_pte_us(vaddr_t, int);
+void sp_tlb_flush_pte_usiii(vaddr_t, int);
 void sp_tlb_flush_all_us(void);
 void sp_tlb_flush_all_usiii(void);
 
@@ -215,7 +215,14 @@
 void smp_tlb_flush_pte(vaddr_t, pmap_t);
 #define	tlb_flush_pte(va,pm)	smp_tlb_flush_pte(va, pm)
 #else
-#define	tlb_flush_pte(va,pm)	sp_tlb_flush_pte(va, (pm)->pm_ctx)
+static __inline__ void
+tlb_flush_pte(vaddr_t va, pmap_t pm)
+{
+	if (CPU_IS_USIII_UP())
+		sp_tlb_flush_pte_usiii(va, pm->pm_ctx);
+	else
+		sp_tlb_flush_pte_usiii(va, pm->pm_ctx);
+}
 #endif
 
 /* Installed physical memory, as discovered during bootstrap. */

Index: src/sys/arch/sparc64/sparc64/db_interface.c
diff -u src/sys/arch/sparc64/sparc64/db_interface.c:1.120 src/sys/arch/sparc64/sparc64/db_interface.c:1.121
--- src/sys/arch/sparc64/sparc64/db_interface.c:1.120	Wed Dec  2 07:55:53 2009
+++ src/sys/arch/sparc64/sparc64/db_interface.c	Tue Feb  2 04:28:56 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: db_interface.c,v 1.120 2009/12/02 07:55:53 mrg Exp $ */
+/*	$NetBSD: db_interface.c,v 1.121 2010/02/02 04:28:56 mrg Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath.  All rights reserved.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.120 2009/12/02 07:55:53 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.121 2010/02/02 04:28:56 mrg Exp $");
 
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
@@ -959,7 +959,10 @@
 				ctx = pmap_ctx(p->p_vmspace->vm_map.pmap);
 			}
 			if (ctx > 0) {
-				switchtoctx(ctx);
+				if (CPU_IS_USIII_UP())
+					switchtoctx_usiii(ctx);
+				else
+					switchtoctx_us(ctx);
 				return;
 			}
 			db_printf("could not activate pmap for PID %ld.\n",

Index: src/sys/arch/sparc64/sparc64/ipifuncs.c
diff -u src/sys/arch/sparc64/sparc64/ipifuncs.c:1.29 src/sys/arch/sparc64/sparc64/ipifuncs.c:1.30
--- src/sys/arch/sparc64/sparc64/ipifuncs.c:1.29	Mon Feb  1 07:01:40 2010
+++ src/sys/arch/sparc64/sparc64/ipifuncs.c	Tue Feb  2 04:28:56 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: ipifuncs.c,v 1.29 2010/02/01 07:01:40 mrg Exp $ */
+/*	$NetBSD: ipifuncs.c,v 1.30 2010/02/02 04:28:56 mrg Exp $ */
 
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.29 2010/02/01 07:01:40 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.30 2010/02/02 04:28:56 mrg Exp $");
 
 #include "opt_ddb.h"
 
@@ -360,8 +360,12 @@
 	/* Flush our own TLB */
 	ctx = pm->pm_ctx[cpu_number()];
 	KASSERT(ctx >= 0);
-	if (kpm || ctx > 0)
-		sp_tlb_flush_pte(va, ctx);
+	if (kpm || ctx > 0) {
+		if (CPU_IS_USIII_UP())
+			sp_tlb_flush_pte_usiii(va, ctx);
+		else
+			sp_tlb_flush_pte_us(va, ctx);
+	}
 
 	CPUSET_ASSIGN(cpuset, cpus_active);
 	CPUSET_DEL(cpuset, cpu_number());

Index: src/sys/arch/sparc64/sparc64/locore.s
diff -u src/sys/arch/sparc64/sparc64/locore.s:1.309 src/sys/arch/sparc64/sparc64/locore.s:1.310
--- src/sys/arch/sparc64/sparc64/locore.s:1.309	Tue Feb  2 03:07:06 2010
+++ src/sys/arch/sparc64/sparc64/locore.s	Tue Feb  2 04:28:56 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.s,v 1.309 2010/02/02 03:07:06 mrg Exp $	*/
+/*	$NetBSD: locore.s,v 1.310 2010/02/02 04:28:56 mrg Exp $	*/
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -3628,7 +3628,7 @@
 #endif
 	andn	%g2, 0xfff, %g2			! drop unused va bits
 	mov	CTX_PRIMARY, %g5
-	ldxa	[%g5] ASI_DMMU, %g6		! Save secondary context
+	ldxa	[%g5] ASI_DMMU, %g6		! Save primary context
 	sethi	%hi(KERNBASE), %g7
 	membar	#LoadStore
 	stxa	%g3, [%g5] ASI_DMMU		! Insert context to demap
@@ -5164,14 +5164,15 @@
 	NOTREACHED
 
 /*
- * sp_tlb_flush_pte(vaddr_t va, int ctx)
+ * sp_tlb_flush_pte_us(vaddr_t va, int ctx)
+ * sp_tlb_flush_pte_usiii(vaddr_t va, int ctx)
  *
  * Flush tte from both IMMU and DMMU.
  *
  * This uses %o0-%o5
  */
 	.align 8
-ENTRY(sp_tlb_flush_pte)
+ENTRY(sp_tlb_flush_pte_us)
 #ifdef DEBUG
 	set	pmapdebug, %o3
 	lduw	[%o3], %o3
@@ -5189,12 +5190,11 @@
 	restore
 	.data
 1:
-	.asciz	"sp_tlb_flush_pte:	demap ctx=%x va=%08x res=%x\r\n"
+	.asciz	"sp_tlb_flush_pte_us:	demap ctx=%x va=%08x res=%x\r\n"
 	_ALIGN
 	.text
 2:
 #endif
-#ifdef	SPITFIRE
 #ifdef MULTIPROCESSOR
 	rdpr	%pstate, %o3
 	andn	%o3, PSTATE_IE, %o4			! disable interrupts
@@ -5225,8 +5225,30 @@
 #else
 	 nop
 #endif
-#else
 
+ENTRY(sp_tlb_flush_pte_usiii)
+#ifdef DEBUG
+	set	pmapdebug, %o3
+	lduw	[%o3], %o3
+!	movrz	%o1, -1, %o3				! Print on either pmapdebug & PDB_DEMAP or ctx == 0
+	btst	0x0020, %o3
+	bz,pt	%icc, 2f
+	 nop
+	save	%sp, -CC64FSZ, %sp
+	set	1f, %o0
+	mov	%i1, %o1
+	andn	%i0, 0xfff, %o3
+	or	%o3, 0x010, %o3
+	call	_C_LABEL(printf)
+	 mov	%i0, %o2
+	restore
+	.data
+1:
+	.asciz	"sp_tlb_flush_pte_usiii:	demap ctx=%x va=%08x res=%x\r\n"
+	_ALIGN
+	.text
+2:
+#endif
 	! %o0 = VA [in]
 	! %o1 = ctx value [in] / KERNBASE
 	! %o2 = CTX_PRIMARY
@@ -5269,7 +5291,6 @@
 1:	
 	retl
 	 wrpr	%o4, %pstate				! restore interrupts
-#endif
 
 
 /*
@@ -9693,24 +9714,38 @@
 	/*
 	 * Switch to context in abs(%o0)
 	 */
-ENTRY(switchtoctx)
-#ifdef SPITFIRE
+ENTRY(switchtoctx_us)
 	set	DEMAP_CTX_SECONDARY, %o3
 	stxa	%o3, [%o3] ASI_DMMU_DEMAP
 	mov	CTX_SECONDARY, %o4
 	stxa	%o3, [%o3] ASI_IMMU_DEMAP
 	membar	#Sync
-	stxa	%o0, [%o4] ASI_DMMU		! Maybe we should invali
+	stxa	%o0, [%o4] ASI_DMMU		! Maybe we should invalid
 	sethi	%hi(KERNBASE), %o2
 	membar	#Sync
 	flush	%o2
 	retl
 	 nop
-#else
-	/* UNIMPLEMENTED */
+
+ENTRY(switchtoctx_usiii)
+	mov	CTX_SECONDARY, %o4
+	ldxa	[%o4] ASI_DMMU, %o2		! Load secondary context
+	mov	CTX_PRIMARY, %o5
+	ldxa	[%o5] ASI_DMMU, %o1		! Save primary context
+	membar	#LoadStore
+	stxa	%o2, [%o5] ASI_DMMU		! Insert secondary for demap
+	membar	#Sync
+	set	DEMAP_CTX_PRIMARY, %o3
+	stxa	%o3, [%o3] ASI_DMMU_DEMAP
+	membar	#Sync
+	stxa	%o0, [%o4] ASI_DMMU		! Maybe we should invalid
+	membar	#Sync
+	stxa	%o1, [%o5] ASI_DMMU		! Restore primary context
+	sethi	%hi(KERNBASE), %o2
+	membar	#Sync
+	flush	%o2
 	retl
 	 nop
-#endif
 
 #ifndef _LP64
 	/*

Index: src/sys/arch/sparc64/sparc64/pmap.c
diff -u src/sys/arch/sparc64/sparc64/pmap.c:1.248 src/sys/arch/sparc64/sparc64/pmap.c:1.249
--- src/sys/arch/sparc64/sparc64/pmap.c:1.248	Mon Feb  1 07:01:40 2010
+++ src/sys/arch/sparc64/sparc64/pmap.c	Tue Feb  2 04:28:56 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.248 2010/02/01 07:01:40 mrg Exp $	*/
+/*	$NetBSD: pmap.c,v 1.249 2010/02/02 04:28:56 mrg Exp $	*/
 /*
  *
  * Copyright (C) 1996-1999 Eduardo Horvath.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.248 2010/02/01 07:01:40 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.249 2010/02/02 04:28:56 mrg Exp $");
 
 #undef	NO_VCACHE /* Don't forget the locked TLB in dostart */
 #define	HWREF
@@ -1852,8 +1852,12 @@
 #ifdef MULTIPROCESSOR
 		if (wasmapped && pmap_is_on_mmu(pm))
 			tlb_flush_pte(va, pm);
-		else
-			sp_tlb_flush_pte(va, pmap_ctx(pm));
+		else {
+			if (CPU_IS_USIII_UP())
+				sp_tlb_flush_pte_usiii(va, pmap_ctx(pm));
+			else
+				sp_tlb_flush_pte_us(va, pmap_ctx(pm));
+		}
 #else
 		tlb_flush_pte(va, pm);
 #endif

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