Module Name: src
Committed By: simonb
Date: Sun Jul 26 08:08:41 UTC 2020
Modified Files:
src/sys/arch/mips/include: asm.h bswap.h bus_dma_defs.h
bus_space_defs.h bus_space_funcs.h cache.h cache_ls2.h
cache_mipsNN.h cache_octeon.h cache_r4k.h cache_r5900.h cache_r5k.h
cachectl.h cdefs.h cpu.h cpu_counter.h cpuregs.h db_machdep.h
ecoff_machdep.h fenv.h float.h frame.h ieeefp.h int_const.h
int_fmtio.h int_limits.h int_mwgwtypes.h intr.h isa_machdep.h
kcore.h kdbparam.h limits.h locore.h math.h mcontext.h mips1_pte.h
mips3_pte.h mipsNN.h mips_opcode.h mips_param.h netbsd32_machdep.h
pci_machdep.h pmap.h proc.h profile.h pte.h ptrace.h r3900regs.h
reg.h regdef.h regnum.h reloc.h setjmp.h sljit_machdep.h sysarch.h
vmparam.h wchar_limits.h wired_map.h
Log Message:
#define<tab>
Nuke trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/include/bswap.h \
src/sys/arch/mips/include/bus_dma_defs.h \
src/sys/arch/mips/include/cache_octeon.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/include/bus_space_defs.h \
src/sys/arch/mips/include/cache_ls2.h src/sys/arch/mips/include/kcore.h \
src/sys/arch/mips/include/wchar_limits.h \
src/sys/arch/mips/include/wired_map.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/include/bus_space_funcs.h \
src/sys/arch/mips/include/sljit_machdep.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/include/cache.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/include/cache_mipsNN.h \
src/sys/arch/mips/include/cache_r5k.h \
src/sys/arch/mips/include/cpu_counter.h src/sys/arch/mips/include/fenv.h \
src/sys/arch/mips/include/int_const.h \
src/sys/arch/mips/include/netbsd32_machdep.h
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/include/cache_r4k.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/mips/include/cache_r5900.h \
src/sys/arch/mips/include/frame.h src/sys/arch/mips/include/int_limits.h \
src/sys/arch/mips/include/reloc.h src/sys/arch/mips/include/setjmp.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/include/cachectl.h \
src/sys/arch/mips/include/ieeefp.h src/sys/arch/mips/include/intr.h \
src/sys/arch/mips/include/sysarch.h
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/include/cdefs.h
cvs rdiff -u -r1.128 -r1.129 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/include/db_machdep.h
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/mips/include/ecoff_machdep.h
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/mips/include/float.h \
src/sys/arch/mips/include/ptrace.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/include/int_fmtio.h \
src/sys/arch/mips/include/int_mwgwtypes.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/include/isa_machdep.h \
src/sys/arch/mips/include/kdbparam.h src/sys/arch/mips/include/mipsNN.h \
src/sys/arch/mips/include/pci_machdep.h
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/mips/include/limits.h
cvs rdiff -u -r1.109 -r1.110 src/sys/arch/mips/include/locore.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/include/math.h \
src/sys/arch/mips/include/r3900regs.h
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/include/mcontext.h
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/mips/include/mips1_pte.h
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/mips/include/mips3_pte.h
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/mips/include/mips_opcode.h \
src/sys/arch/mips/include/profile.h
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/mips/include/mips_param.h
cvs rdiff -u -r1.71 -r1.72 src/sys/arch/mips/include/pmap.h
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/mips/include/proc.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/mips/include/pte.h
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/reg.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/include/regdef.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/include/regnum.h
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/mips/include/vmparam.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.56 src/sys/arch/mips/include/asm.h:1.57
--- src/sys/arch/mips/include/asm.h:1.56 Fri Apr 17 14:19:43 2020
+++ src/sys/arch/mips/include/asm.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.56 2020/04/17 14:19:43 joerg Exp $ */
+/* $NetBSD: asm.h,v 1.57 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -267,7 +267,7 @@ _C_LABEL(x):
.asciz str; \
.align 3
-#define RCSID(x) .pushsection ".ident","MS",@progbits,1; \
+#define RCSID(x) .pushsection ".ident","MS",@progbits,1; \
.asciz x; \
.popsection
@@ -515,9 +515,9 @@ _C_LABEL(x):
/* CPU dependent hook for cp0 load delays */
#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
-#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
+#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
#else
-#define MFC0_HAZARD /* nothing */
+#define MFC0_HAZARD /* nothing */
#endif
#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
Index: src/sys/arch/mips/include/bswap.h
diff -u src/sys/arch/mips/include/bswap.h:1.4 src/sys/arch/mips/include/bswap.h:1.5
--- src/sys/arch/mips/include/bswap.h:1.4 Thu May 23 21:39:49 2013
+++ src/sys/arch/mips/include/bswap.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bswap.h,v 1.4 2013/05/23 21:39:49 christos Exp $ */
+/* $NetBSD: bswap.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -28,7 +28,7 @@
#ifndef _MIPS_BSWAP_H_
#define _MIPS_BSWAP_H_
-#define __BSWAP_RENAME
+#define __BSWAP_RENAME
#include <sys/bswap.h>
#endif /* !_MIPS_BSWAP_H_ */
Index: src/sys/arch/mips/include/bus_dma_defs.h
diff -u src/sys/arch/mips/include/bus_dma_defs.h:1.4 src/sys/arch/mips/include/bus_dma_defs.h:1.5
--- src/sys/arch/mips/include/bus_dma_defs.h:1.4 Thu Feb 7 04:32:54 2019
+++ src/sys/arch/mips/include/bus_dma_defs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma_defs.h,v 1.4 2019/02/07 04:32:54 mrg Exp $ */
+/* $NetBSD: bus_dma_defs.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -82,7 +82,7 @@
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
-#define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow
+#define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow
* things like write combining */
/*
@@ -278,7 +278,7 @@ extern const struct mips_bus_dmatag_ops
.dmamap_sync = _bus_dmamap_sync, \
}
-#define _BUS_DMAMEM_OPS_INITIALIZER { \
+#define _BUS_DMAMEM_OPS_INITIALIZER { \
.dmamem_alloc = _bus_dmamem_alloc, \
.dmamem_free = _bus_dmamem_free, \
.dmamem_map = _bus_dmamem_map, \
@@ -286,7 +286,7 @@ extern const struct mips_bus_dmatag_ops
.dmamem_mmap = _bus_dmamem_mmap, \
}
-#define _BUS_DMATAG_OPS_INITIALIZER { \
+#define _BUS_DMATAG_OPS_INITIALIZER { \
.dmatag_subregion = _bus_dmatag_subregion, \
.dmatag_destroy = _bus_dmatag_destroy, \
}
Index: src/sys/arch/mips/include/cache_octeon.h
diff -u src/sys/arch/mips/include/cache_octeon.h:1.4 src/sys/arch/mips/include/cache_octeon.h:1.5
--- src/sys/arch/mips/include/cache_octeon.h:1.4 Sun Jun 14 08:43:07 2020
+++ src/sys/arch/mips/include/cache_octeon.h Sun Jul 26 08:08:41 2020
@@ -1,7 +1,7 @@
-/* $NetBSD: cache_octeon.h,v 1.4 2020/06/14 08:43:07 simonb Exp $ */
+/* $NetBSD: cache_octeon.h,v 1.5 2020/07/26 08:08:41 simonb Exp $ */
#ifndef _MIPS_CACHE_OCTEON_H_
-#define _MIPS_CACHE_OCTEON_H_
+#define _MIPS_CACHE_OCTEON_H_
#define CACHE_OCTEON_I 0
#define CACHE_OCTEON_D 1
Index: src/sys/arch/mips/include/bus_space_defs.h
diff -u src/sys/arch/mips/include/bus_space_defs.h:1.3 src/sys/arch/mips/include/bus_space_defs.h:1.4
--- src/sys/arch/mips/include/bus_space_defs.h:1.3 Thu Sep 15 21:45:37 2016
+++ src/sys/arch/mips/include/bus_space_defs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_defs.h,v 1.3 2016/09/15 21:45:37 jdolecek Exp $ */
+/* $NetBSD: bus_space_defs.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -95,10 +95,10 @@
(void) 0; \
})
-#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
+#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
#else
#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0
-#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
+#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#endif /* BUS_SPACE_DEBUG */
#endif /* _KERNEL */
@@ -184,7 +184,7 @@ struct mips_bus_space {
uint32_t *, bus_size_t);
void (*bs_rm_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* read region */
void (*bs_rr_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
@@ -194,7 +194,7 @@ struct mips_bus_space {
uint32_t *, bus_size_t);
void (*bs_rr_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* write (single) */
void (*bs_w_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t);
@@ -214,7 +214,7 @@ struct mips_bus_space {
const uint32_t *, bus_size_t);
void (*bs_wm_8)(void *, bus_space_handle_t, bus_size_t,
const uint64_t *, bus_size_t);
-
+
/* write region */
void (*bs_wr_1)(void *, bus_space_handle_t, bus_size_t,
const uint8_t *, bus_size_t);
@@ -240,7 +240,7 @@ struct mips_bus_space {
uint32_t *, bus_size_t);
void (*bs_rms_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* read region stream */
void (*bs_rrs_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
@@ -250,7 +250,7 @@ struct mips_bus_space {
uint32_t *, bus_size_t);
void (*bs_rrs_8)(void *, bus_space_handle_t, bus_size_t,
uint64_t *, bus_size_t);
-
+
/* write (single) stream */
void (*bs_ws_1)(void *, bus_space_handle_t, bus_size_t,
uint8_t);
@@ -270,7 +270,7 @@ struct mips_bus_space {
const uint32_t *, bus_size_t);
void (*bs_wms_8)(void *, bus_space_handle_t, bus_size_t,
const uint64_t *, bus_size_t);
-
+
/* write region stream */
void (*bs_wrs_1)(void *, bus_space_handle_t, bus_size_t,
const uint8_t *, bus_size_t);
Index: src/sys/arch/mips/include/cache_ls2.h
diff -u src/sys/arch/mips/include/cache_ls2.h:1.3 src/sys/arch/mips/include/cache_ls2.h:1.4
--- src/sys/arch/mips/include/cache_ls2.h:1.3 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_ls2.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_ls2.h,v 1.3 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_ls2.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_CACHE_LS2_H_
-#define _MIPS_CACHE_LS2_H_
+#define _MIPS_CACHE_LS2_H_
/*
* Cache definitions/operations for Loongson-style caches.
@@ -48,7 +48,7 @@
* The way is encoded in the bottom 2 bits of VA.
*/
-#define cache_op_ls2_8line_4way(va, op) \
+#define cache_op_ls2_8line_4way(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
@@ -72,7 +72,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_line_4way(va, op) \
+#define cache_op_ls2_line_4way(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0(%0); cache %1, 1(%0) \n\t" \
@@ -82,7 +82,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_8line(va, op) \
+#define cache_op_ls2_8line(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
@@ -94,7 +94,7 @@
: "r" (va), "i" (op) \
: "memory");
-#define cache_op_ls2_line(va, op) \
+#define cache_op_ls2_line(va, op) \
__asm volatile( \
".set noreorder \n\t" \
"cache %1, 0(%0) \n\t" \
Index: src/sys/arch/mips/include/kcore.h
diff -u src/sys/arch/mips/include/kcore.h:1.3 src/sys/arch/mips/include/kcore.h:1.4
--- src/sys/arch/mips/include/kcore.h:1.3 Fri Jun 12 16:28:39 2015
+++ src/sys/arch/mips/include/kcore.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: kcore.h,v 1.3 2015/06/12 16:28:39 matt Exp $ */
+/* $NetBSD: kcore.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -33,7 +33,7 @@
*/
#ifndef _MIPS_KCORE_H_
-#define _MIPS_KCORE_H_
+#define _MIPS_KCORE_H_
typedef struct cpu_kcore_hdr {
uint64_t sysmappa; /* PA of Sysmap */
Index: src/sys/arch/mips/include/wchar_limits.h
diff -u src/sys/arch/mips/include/wchar_limits.h:1.3 src/sys/arch/mips/include/wchar_limits.h:1.4
--- src/sys/arch/mips/include/wchar_limits.h:1.3 Mon Apr 28 20:23:28 2008
+++ src/sys/arch/mips/include/wchar_limits.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: wchar_limits.h,v 1.3 2008/04/28 20:23:28 martin Exp $ */
+/* $NetBSD: wchar_limits.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_WCHAR_LIMITS_H_
-#define _MIPS_WCHAR_LIMITS_H_
+#define _MIPS_WCHAR_LIMITS_H_
/*
* 7.18.3 Limits of other integer types
Index: src/sys/arch/mips/include/wired_map.h
diff -u src/sys/arch/mips/include/wired_map.h:1.3 src/sys/arch/mips/include/wired_map.h:1.4
--- src/sys/arch/mips/include/wired_map.h:1.3 Wed Feb 21 22:59:47 2007
+++ src/sys/arch/mips/include/wired_map.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: wired_map.h,v 1.3 2007/02/21 22:59:47 thorpej Exp $ */
+/* $NetBSD: wired_map.h,v 1.4 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2005 Tadpole Computer Inc.
@@ -32,7 +32,7 @@
*/
#ifndef _MIPS_WIRED_MAP_H
-#define _MIPS_WIRED_MAP_H
+#define _MIPS_WIRED_MAP_H
/*
* Certain machines have peripheral busses which are only accessible
@@ -62,12 +62,12 @@
*/
#ifndef MIPS3_WIRED_SIZE
-#define MIPS3_WIRED_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)
+#define MIPS3_WIRED_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(MIPS3_PG_SIZE_16M)
#endif
-#define MIPS3_WIRED_OFFMASK (MIPS3_WIRED_SIZE - 1)
+#define MIPS3_WIRED_OFFMASK (MIPS3_WIRED_SIZE - 1)
-#define MIPS3_WIRED_ENTRY_SIZE(pgsize) ((pgsize) * 2)
-#define MIPS3_WIRED_ENTRY_OFFMASK(pgsize) (MIPS3_WIRED_ENTRY_SIZE(pgsize) - 1)
+#define MIPS3_WIRED_ENTRY_SIZE(pgsize) ((pgsize) * 2)
+#define MIPS3_WIRED_ENTRY_OFFMASK(pgsize) (MIPS3_WIRED_ENTRY_SIZE(pgsize) - 1)
/*
* This defines the maximum number of wired TLB entries that the wired
@@ -77,7 +77,7 @@
* and that is not included in this number.
*/
#ifndef MIPS3_NWIRED_ENTRY
-#define MIPS3_NWIRED_ENTRY 8 /* upper limit */
+#define MIPS3_NWIRED_ENTRY 8 /* upper limit */
#endif
struct wired_map_entry {
Index: src/sys/arch/mips/include/bus_space_funcs.h
diff -u src/sys/arch/mips/include/bus_space_funcs.h:1.1 src/sys/arch/mips/include/bus_space_funcs.h:1.2
--- src/sys/arch/mips/include/bus_space_funcs.h:1.1 Fri Jul 1 17:28:55 2011
+++ src/sys/arch/mips/include/bus_space_funcs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_funcs.h,v 1.1 2011/07/01 17:28:55 dyoung Exp $ */
+/* $NetBSD: bus_space_funcs.h,v 1.2 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@@ -129,7 +129,7 @@ do { \
/*
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
*/
-#define bus_space_vaddr(t, h) \
+#define bus_space_vaddr(t, h) \
(*(t)->bs_vaddr)((t)->bs_cookie, (h))
/*
Index: src/sys/arch/mips/include/sljit_machdep.h
diff -u src/sys/arch/mips/include/sljit_machdep.h:1.1 src/sys/arch/mips/include/sljit_machdep.h:1.2
--- src/sys/arch/mips/include/sljit_machdep.h:1.1 Wed Jul 23 18:19:44 2014
+++ src/sys/arch/mips/include/sljit_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sljit_machdep.h,v 1.1 2014/07/23 18:19:44 alnsn Exp $ */
+/* $NetBSD: sljit_machdep.h,v 1.2 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2012,2014 The NetBSD Foundation, Inc.
@@ -27,12 +27,12 @@
*/
#ifndef _MIPS_SLJITARCH_H
-#define _MIPS_SLJITARCH_H
+#define _MIPS_SLJITARCH_H
#ifdef _LP64
-#define SLJIT_CONFIG_MIPS_64 1
+#define SLJIT_CONFIG_MIPS_64 1
#else
-#define SLJIT_CONFIG_MIPS_32 1
+#define SLJIT_CONFIG_MIPS_32 1
#endif
#include <sys/types.h>
@@ -40,12 +40,12 @@
#ifdef _KERNEL
#include <mips/cache.h>
-#define SLJIT_CACHE_FLUSH(from, to) mips_icache_sync_range( \
+#define SLJIT_CACHE_FLUSH(from, to) mips_icache_sync_range( \
(vaddr_t)(from), (vsize_t)((const char *)(to) - (const char *)(from)))
#else
#include <mips/cachectl.h>
-#define SLJIT_CACHE_FLUSH(from, to) \
+#define SLJIT_CACHE_FLUSH(from, to) \
(void)_cacheflush((void*)(from), (size_t)((to) - (from)), ICACHE)
#endif
Index: src/sys/arch/mips/include/cache.h
diff -u src/sys/arch/mips/include/cache.h:1.14 src/sys/arch/mips/include/cache.h:1.15
--- src/sys/arch/mips/include/cache.h:1.14 Thu Aug 18 22:23:20 2016
+++ src/sys/arch/mips/include/cache.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.14 2016/08/18 22:23:20 skrll Exp $ */
+/* $NetBSD: cache.h,v 1.15 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#ifndef _MIPS_CACHE_H_
-#define _MIPS_CACHE_H_
+#define _MIPS_CACHE_H_
/*
* Cache operations.
Index: src/sys/arch/mips/include/cache_mipsNN.h
diff -u src/sys/arch/mips/include/cache_mipsNN.h:1.5 src/sys/arch/mips/include/cache_mipsNN.h:1.6
--- src/sys/arch/mips/include/cache_mipsNN.h:1.5 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_mipsNN.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_mipsNN.h,v 1.5 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_mipsNN.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#ifndef _MIPS_CACHE_MIPSNN_H_
-#define _MIPS_CACHE_MIPSNN_H_
+#define _MIPS_CACHE_MIPSNN_H_
void mipsNN_cache_init(uint32_t, uint32_t);
Index: src/sys/arch/mips/include/cache_r5k.h
diff -u src/sys/arch/mips/include/cache_r5k.h:1.5 src/sys/arch/mips/include/cache_r5k.h:1.6
--- src/sys/arch/mips/include/cache_r5k.h:1.5 Sun Jun 14 15:12:56 2020
+++ src/sys/arch/mips/include/cache_r5k.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5k.h,v 1.5 2020/06/14 15:12:56 tsutsui Exp $ */
+/* $NetBSD: cache_r5k.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -62,12 +62,12 @@ void r5k_sdcache_wb_range(register_t, vs
#endif /* _KERNEL && !_LOCORE */
-#define CACHEOP_R5K_Page_Invalidate_S 0x17
+#define CACHEOP_R5K_Page_Invalidate_S 0x17
-#define R5K_SC_LINESIZE 32
-#define R5K_SC_PAGESIZE (R5K_SC_LINESIZE * 128)
-#define R5K_SC_PAGEMASK (R5K_SC_PAGESIZE - 1)
+#define R5K_SC_LINESIZE 32
+#define R5K_SC_PAGESIZE (R5K_SC_LINESIZE * 128)
+#define R5K_SC_PAGEMASK (R5K_SC_PAGESIZE - 1)
-#define mips_r5k_round_page(x) (((x) + (register_t)R5K_SC_PAGEMASK) \
+#define mips_r5k_round_page(x) (((x) + (register_t)R5K_SC_PAGEMASK) \
& (register_t)R5K_SC_PAGEMASK)
-#define mips_r5k_trunc_page(x) ((x) & (register_t)R5K_SC_PAGEMASK)
+#define mips_r5k_trunc_page(x) ((x) & (register_t)R5K_SC_PAGEMASK)
Index: src/sys/arch/mips/include/cpu_counter.h
diff -u src/sys/arch/mips/include/cpu_counter.h:1.5 src/sys/arch/mips/include/cpu_counter.h:1.6
--- src/sys/arch/mips/include/cpu_counter.h:1.5 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cpu_counter.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_counter.h,v 1.5 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -26,7 +26,7 @@
*/
#ifndef _MIPS_CPU_COUNTER_H_
-#define _MIPS_CPU_COUNTER_H_
+#define _MIPS_CPU_COUNTER_H_
/*
* Machine-specific support for CPU counter.
@@ -54,12 +54,12 @@ cpu_hascounter(void)
}
#if __mips >= 3 || !defined(__mips_o32) || defined(MIPS3_PLUS)
-#define cpu_counter() cpu_counter32()
+#define cpu_counter() cpu_counter32()
uint32_t cpu_counter32(void); /* weak alias of mips3_cp0_count_read */
#else
#define cpu_counter() (0)
-#define cpu_counter32() (0)
+#define cpu_counter32() (0)
#endif
static __inline uint64_t
Index: src/sys/arch/mips/include/fenv.h
diff -u src/sys/arch/mips/include/fenv.h:1.5 src/sys/arch/mips/include/fenv.h:1.6
--- src/sys/arch/mips/include/fenv.h:1.5 Tue Oct 29 04:55:36 2019
+++ src/sys/arch/mips/include/fenv.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fenv.h,v 1.5 2019/10/29 04:55:36 christos Exp $ */
+/* $NetBSD: fenv.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2004-2005 David Schultz <d...@freebsd.org>
@@ -68,7 +68,7 @@ extern const fenv_t __fe_dfl_env;
/* We need to be able to map status flag positions to mask flag positions */
#define _ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
-#define _ENABLE_SHIFT 5
+#define _ENABLE_SHIFT 5
static inline fpu_control_t
__rfs(void)
Index: src/sys/arch/mips/include/int_const.h
diff -u src/sys/arch/mips/include/int_const.h:1.5 src/sys/arch/mips/include/int_const.h:1.6
--- src/sys/arch/mips/include/int_const.h:1.5 Wed Aug 13 22:51:58 2014
+++ src/sys/arch/mips/include/int_const.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: int_const.h,v 1.5 2014/08/13 22:51:58 matt Exp $ */
+/* $NetBSD: int_const.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_INT_CONST_H_
-#define _MIPS_INT_CONST_H_
+#define _MIPS_INT_CONST_H_
#ifdef __INTMAX_C_SUFFIX__
#include <sys/common_int_const.h>
Index: src/sys/arch/mips/include/netbsd32_machdep.h
diff -u src/sys/arch/mips/include/netbsd32_machdep.h:1.5 src/sys/arch/mips/include/netbsd32_machdep.h:1.6
--- src/sys/arch/mips/include/netbsd32_machdep.h:1.5 Tue Oct 31 12:37:23 2017
+++ src/sys/arch/mips/include/netbsd32_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: netbsd32_machdep.h,v 1.5 2017/10/31 12:37:23 martin Exp $ */
+/* $NetBSD: netbsd32_machdep.h,v 1.6 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MACHINE_NETBSD32_H_
-#define _MACHINE_NETBSD32_H_
+#define _MACHINE_NETBSD32_H_
#include <sys/types.h>
@@ -40,7 +40,7 @@
#define NETBSD32_POINTER_TYPE int32_t
typedef struct { NETBSD32_POINTER_TYPE i32; } netbsd32_pointer_t;
-#define NETBSD32_INT64_ALIGN
+#define NETBSD32_INT64_ALIGN
typedef netbsd32_pointer_t netbsd32_sigcontextp_t;
Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.16 src/sys/arch/mips/include/cache_r4k.h:1.17
--- src/sys/arch/mips/include/cache_r4k.h:1.16 Tue Jul 12 15:56:23 2016
+++ src/sys/arch/mips/include/cache_r4k.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r4k.h,v 1.16 2016/07/12 15:56:23 skrll Exp $ */
+/* $NetBSD: cache_r4k.h,v 1.17 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -63,7 +63,7 @@
*
* Perform the specified cache operation on a single line.
*/
-#define cache_op_r4k_line(va, op) \
+#define cache_op_r4k_line(va, op) \
{ \
__asm volatile( \
".set push" "\n\t" \
@@ -120,7 +120,7 @@ cache_r4k_op_8lines_NN(size_t n, registe
*
* Perform the specified cache operation on 32 n-byte cache lines.
*/
-#define cache_r4k_op_32lines_NN(n, va, op) \
+#define cache_r4k_op_32lines_NN(n, va, op) \
{ \
__asm volatile( \
".set push" "\n\t" \
@@ -327,7 +327,7 @@ void cache_r4k_sdcache_index_wb_inv_16(v
void cache_r4k_sdcache_hit_inv_16(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_16(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_16(register_t, vsize_t);
-
+
/* cache_r4k_pcache32.S */
void cache_r4k_icache_index_inv_32(vaddr_t, vsize_t);
@@ -343,7 +343,7 @@ void cache_r4k_sdcache_index_wb_inv_32(v
void cache_r4k_sdcache_hit_inv_32(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_32(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_32(register_t, vsize_t);
-
+
/* cache_r4k_pcache64.S */
void cache_r4k_icache_index_inv_64(vaddr_t, vsize_t);
@@ -359,7 +359,7 @@ void cache_r4k_sdcache_index_wb_inv_64(v
void cache_r4k_sdcache_hit_inv_64(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_64(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_64(register_t, vsize_t);
-
+
/* cache_r4k_pcache128.S */
void cache_r4k_icache_index_inv_128(vaddr_t, vsize_t);
@@ -375,5 +375,5 @@ void cache_r4k_sdcache_index_wb_inv_128(
void cache_r4k_sdcache_hit_inv_128(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_128(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_128(register_t, vsize_t);
-
+
#endif /* !_LOCORE */
Index: src/sys/arch/mips/include/cache_r5900.h
diff -u src/sys/arch/mips/include/cache_r5900.h:1.9 src/sys/arch/mips/include/cache_r5900.h:1.10
--- src/sys/arch/mips/include/cache_r5900.h:1.9 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/cache_r5900.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5900.h,v 1.9 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: cache_r5900.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -29,24 +29,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#define CACHE_R5900_SIZE_I 16384
+#define CACHE_R5900_SIZE_I 16384
#define CACHE_R5900_SIZE_D 8192
-#define CACHE_R5900_LSIZE_I 64
-#define CACHE_R5900_LSIZE_D 64
+#define CACHE_R5900_LSIZE_I 64
+#define CACHE_R5900_LSIZE_D 64
-#define CACHEOP_R5900_IINV_I 0x07 /* INDEX INVALIDATE */
-#define CACHEOP_R5900_HINV_I 0x0b /* HIT INVALIDATE */
-#define CACHEOP_R5900_IWBINV_D 0x14
+#define CACHEOP_R5900_IINV_I 0x07 /* INDEX INVALIDATE */
+#define CACHEOP_R5900_HINV_I 0x0b /* HIT INVALIDATE */
+#define CACHEOP_R5900_IWBINV_D 0x14
/* INDEX WRITE BACK INVALIDATE */
-#define CACHEOP_R5900_ILTG_D 0x10 /* INDEX LOAD TAG */
-#define CACHEOP_R5900_ISTG_D 0x12 /* INDEX STORE TAG */
-#define CACHEOP_R5900_IINV_D 0x16 /* INDEX INVALIDATE */
-#define CACHEOP_R5900_HINV_D 0x1a /* HIT INVALIDATE */
-#define CACHEOP_R5900_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */
-#define CACHEOP_R5900_ILDT_D 0x11 /* INDEX LOAD DATA */
-#define CACHEOP_R5900_ISDT_D 0x13 /* INDEX STORE DATA */
-#define CACHEOP_R5900_HWB_D 0x1c
+#define CACHEOP_R5900_ILTG_D 0x10 /* INDEX LOAD TAG */
+#define CACHEOP_R5900_ISTG_D 0x12 /* INDEX STORE TAG */
+#define CACHEOP_R5900_IINV_D 0x16 /* INDEX INVALIDATE */
+#define CACHEOP_R5900_HINV_D 0x1a /* HIT INVALIDATE */
+#define CACHEOP_R5900_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */
+#define CACHEOP_R5900_ILDT_D 0x11 /* INDEX LOAD DATA */
+#define CACHEOP_R5900_ISDT_D 0x13 /* INDEX STORE DATA */
+#define CACHEOP_R5900_HWB_D 0x1c
/* HIT WRITEBACK W/O INVALIDATE */
#if !defined(_LOCORE)
Index: src/sys/arch/mips/include/frame.h
diff -u src/sys/arch/mips/include/frame.h:1.9 src/sys/arch/mips/include/frame.h:1.10
--- src/sys/arch/mips/include/frame.h:1.9 Sun Feb 19 21:06:16 2012
+++ src/sys/arch/mips/include/frame.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.9 2012/02/19 21:06:16 rmind Exp $ */
+/* $NetBSD: frame.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_FRAME_H_
-#define _MIPS_FRAME_H_
+#define _MIPS_FRAME_H_
#ifndef _LOCORE
@@ -49,5 +49,5 @@ void sendsig_sigcontext(const ksiginfo_t
#endif /* _LOCORE */
#endif /* _MIPS_FRAME_H_ */
-
+
/* End of frame.h */
Index: src/sys/arch/mips/include/int_limits.h
diff -u src/sys/arch/mips/include/int_limits.h:1.9 src/sys/arch/mips/include/int_limits.h:1.10
--- src/sys/arch/mips/include/int_limits.h:1.9 Wed Aug 13 22:31:07 2014
+++ src/sys/arch/mips/include/int_limits.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: int_limits.h,v 1.9 2014/08/13 22:31:07 matt Exp $ */
+/* $NetBSD: int_limits.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_INT_LIMITS_H_
-#define _MIPS_INT_LIMITS_H_
+#define _MIPS_INT_LIMITS_H_
#ifdef __SIG_ATOMIC_MAX__
#include <sys/common_int_limits.h>
@@ -104,7 +104,7 @@
#endif
/* 7.18.2.3 Limits of fastest minimum-width integer types */
-
+
/* minimum values of fastest minimum-width signed integer types */
#define INT_FAST8_MIN (-0x7fffffff-1) /* int_fast8_t */
#define INT_FAST16_MIN (-0x7fffffff-1) /* int_fast16_t */
Index: src/sys/arch/mips/include/reloc.h
diff -u src/sys/arch/mips/include/reloc.h:1.9 src/sys/arch/mips/include/reloc.h:1.10
--- src/sys/arch/mips/include/reloc.h:1.9 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/include/reloc.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reloc.h,v 1.9 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: reloc.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -34,7 +34,7 @@
*/
#ifndef __MIPS_RELOC_H__
-#define __MIPS_RELOC_H__
+#define __MIPS_RELOC_H__
/*
* MIPS relocation types.
*/
@@ -69,5 +69,5 @@ struct reloc_info_mips {
long r_addend; /* value to add to symbol value */
};
-#define relocation_info reloc_info_mips
+#define relocation_info reloc_info_mips
#endif /* __MIPS_RELOC_H__ */
Index: src/sys/arch/mips/include/setjmp.h
diff -u src/sys/arch/mips/include/setjmp.h:1.9 src/sys/arch/mips/include/setjmp.h:1.10
--- src/sys/arch/mips/include/setjmp.h:1.9 Mon Dec 14 00:46:05 2009
+++ src/sys/arch/mips/include/setjmp.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: setjmp.h,v 1.9 2009/12/14 00:46:05 matt Exp $ */
+/* $NetBSD: setjmp.h,v 1.10 2020/07/26 08:08:41 simonb Exp $ */
/*
* mips/setjmp.h: machine dependent setjmp-related information.
@@ -7,7 +7,7 @@
* struct sigcontext to restore it.
*/
-#define _JBLEN 87 /* XXX Naively 84; 87 for compatibility */
+#define _JBLEN 87 /* XXX Naively 84; 87 for compatibility */
#ifdef __mips_n32
#define _BSD_JBSLOT_T_ long long
#endif
Index: src/sys/arch/mips/include/cachectl.h
diff -u src/sys/arch/mips/include/cachectl.h:1.10 src/sys/arch/mips/include/cachectl.h:1.11
--- src/sys/arch/mips/include/cachectl.h:1.10 Thu Mar 29 21:20:08 2012
+++ src/sys/arch/mips/include/cachectl.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cachectl.h,v 1.10 2012/03/29 21:20:08 christos Exp $ */
+/* $NetBSD: cachectl.h,v 1.11 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_CACHECTL_H_
-#define _MIPS_CACHECTL_H_
+#define _MIPS_CACHECTL_H_
#include <sys/cdefs.h>
@@ -42,16 +42,16 @@ int _cacheflush(void *, size_t, int);
int cacheflush(void *, size_t, int);
/* cacheflush() flags: */
-#define ICACHE 0x01 /* invalidate I-cache */
-#define DCACHE 0x02 /* writeback and invalidate D-cache */
-#define BCACHE (ICACHE|DCACHE) /* invalidate both caches, as above */
+#define ICACHE 0x01 /* invalidate I-cache */
+#define DCACHE 0x02 /* writeback and invalidate D-cache */
+#define BCACHE (ICACHE|DCACHE) /* invalidate both caches, as above */
int cachectl(void *, size_t, int);
/* cachectl() cache operations: */
-#define CACHEABLE 0x00 /* make page(s) cacheable */
-#define UNCACHEABLE 0x01 /* make page(s) uncacheable */
+#define CACHEABLE 0x00 /* make page(s) cacheable */
+#define UNCACHEABLE 0x01 /* make page(s) uncacheable */
__END_DECLS
Index: src/sys/arch/mips/include/ieeefp.h
diff -u src/sys/arch/mips/include/ieeefp.h:1.10 src/sys/arch/mips/include/ieeefp.h:1.11
--- src/sys/arch/mips/include/ieeefp.h:1.10 Wed Mar 22 23:11:09 2017
+++ src/sys/arch/mips/include/ieeefp.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ieeefp.h,v 1.10 2017/03/22 23:11:09 chs Exp $ */
+/* $NetBSD: ieeefp.h,v 1.11 2020/07/26 08:08:41 simonb Exp $ */
/*
* Written by J.T. Conklin, Apr 11, 1995
@@ -6,7 +6,7 @@
*/
#ifndef _MIPS_IEEEFP_H_
-#define _MIPS_IEEEFP_H_
+#define _MIPS_IEEEFP_H_
#include <sys/featuretest.h>
@@ -18,17 +18,17 @@
typedef unsigned int fp_except;
-/* adjust for FP_* and FE_* value differences */
+/* adjust for FP_* and FE_* value differences */
#define __FPE(x) ((x) >> 2)
#define __FEE(x) ((x) << 2)
#define __FPR(x) ((x))
#define __FER(x) ((x))
-#define FP_X_IMP __FPE(FE_INEXACT) /* imprecise (loss of precision) */
-#define FP_X_UFL __FPE(FE_UNDERFLOW) /* underflow exception */
-#define FP_X_OFL __FPE(FE_OVERFLOW) /* overflow exception */
-#define FP_X_DZ __FPE(FE_DIVBYZERO) /* divide-by-zero exception */
-#define FP_X_INV __FPE(FE_INVALID) /* invalid operation exception */
+#define FP_X_IMP __FPE(FE_INEXACT) /* imprecise (loss of precision) */
+#define FP_X_UFL __FPE(FE_UNDERFLOW) /* underflow exception */
+#define FP_X_OFL __FPE(FE_OVERFLOW) /* overflow exception */
+#define FP_X_DZ __FPE(FE_DIVBYZERO) /* divide-by-zero exception */
+#define FP_X_INV __FPE(FE_INVALID) /* invalid operation exception */
typedef enum {
FP_RN=FE_TONEAREST, /* round to nearest representable number */
Index: src/sys/arch/mips/include/intr.h
diff -u src/sys/arch/mips/include/intr.h:1.10 src/sys/arch/mips/include/intr.h:1.11
--- src/sys/arch/mips/include/intr.h:1.10 Sat Jun 6 04:31:52 2015
+++ src/sys/arch/mips/include/intr.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.10 2015/06/06 04:31:52 matt Exp $ */
+/* $NetBSD: intr.h,v 1.11 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -64,7 +64,7 @@
#define IST_LEVEL_HIGH 4 /* level triggered, active high */
#define IST_LEVEL_LOW 5 /* level triggered, active low */
-#define IST_MPSAFE 0x100 /* interrupt is MPSAFE */
+#define IST_MPSAFE 0x100 /* interrupt is MPSAFE */
#define IPI_NOP 0 /* do nothing, interrupt only */
#define IPI_AST 1 /* force ast */
@@ -113,8 +113,8 @@ typedef struct {
#ifdef _KERNEL
#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
-#define __HAVE_PREEMPTION 1
-#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
+#define __HAVE_PREEMPTION 1
+#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
#endif
#ifdef __INTR_PRIVATE
Index: src/sys/arch/mips/include/sysarch.h
diff -u src/sys/arch/mips/include/sysarch.h:1.10 src/sys/arch/mips/include/sysarch.h:1.11
--- src/sys/arch/mips/include/sysarch.h:1.10 Thu May 23 21:39:49 2013
+++ src/sys/arch/mips/include/sysarch.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysarch.h,v 1.10 2013/05/23 21:39:49 christos Exp $ */
+/* $NetBSD: sysarch.h,v 1.11 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -26,13 +26,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MIPS_SYSARCH_H_
-#define _MIPS_SYSARCH_H_
+#define _MIPS_SYSARCH_H_
/*
* Architecture specific syscalls (mips)
*/
-#define MIPS_CACHEFLUSH 0
-#define MIPS_CACHECTL 1
+#define MIPS_CACHEFLUSH 0
+#define MIPS_CACHECTL 1
struct mips_cacheflush_args {
vaddr_t va;
Index: src/sys/arch/mips/include/cdefs.h
diff -u src/sys/arch/mips/include/cdefs.h:1.15 src/sys/arch/mips/include/cdefs.h:1.16
--- src/sys/arch/mips/include/cdefs.h:1.15 Tue Mar 18 17:11:19 2014
+++ src/sys/arch/mips/include/cdefs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cdefs.h,v 1.15 2014/03/18 17:11:19 christos Exp $ */
+/* $NetBSD: cdefs.h,v 1.16 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1995 Carnegie-Mellon University.
@@ -34,16 +34,16 @@
* These are depreciated. Use __mips_{o32,o64,n32,n64} instead.
*/
/* MIPS Subprogram Interface Model */
-#define _MIPS_SIM_ABIX32 4 /* 64 bit safe, ILP32 o32 model */
-#define _MIPS_SIM_ABI64 3
-#define _MIPS_SIM_NABI32 2 /* 64bit safe, ILP32 n32 model */
-#define _MIPS_SIM_ABI32 1
+#define _MIPS_SIM_ABIX32 4 /* 64 bit safe, ILP32 o32 model */
+#define _MIPS_SIM_ABI64 3
+#define _MIPS_SIM_NABI32 2 /* 64bit safe, ILP32 n32 model */
+#define _MIPS_SIM_ABI32 1
-#define _MIPS_BSD_API_LP32 _MIPS_SIM_ABI32
+#define _MIPS_BSD_API_LP32 _MIPS_SIM_ABI32
#define _MIPS_BSD_API_LP32_64CLEAN _MIPS_SIM_ABIX32
#define _MIPS_BSD_API_LP64 _MIPS_SIM_ABI64
-#define _MIPS_BSD_API_O32 _MIPS_SIM_ABI32
+#define _MIPS_BSD_API_O32 _MIPS_SIM_ABI32
#define _MIPS_BSD_API_O64 _MIPS_SIM_ABIX32
#define _MIPS_BSD_API_N32 _MIPS_SIM_NABI32
#define _MIPS_BSD_API_N64 _MIPS_SIM_ABI64
Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.128 src/sys/arch/mips/include/cpu.h:1.129
--- src/sys/arch/mips/include/cpu.h:1.128 Sun Dec 1 15:34:44 2019
+++ src/sys/arch/mips/include/cpu.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.128 2019/12/01 15:34:44 ad Exp $ */
+/* $NetBSD: cpu.h,v 1.129 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -35,7 +35,7 @@
*/
#ifndef _CPU_H_
-#define _CPU_H_
+#define _CPU_H_
/*
* Exported definitions unique to NetBSD/mips cpu support.
@@ -66,14 +66,14 @@ typedef struct cpu_watchpoint {
} cpu_watchpoint_t;
/* (abstract) mode bits */
-#define CPUWATCH_WRITE __BIT(0)
-#define CPUWATCH_READ __BIT(1)
-#define CPUWATCH_EXEC __BIT(2)
-#define CPUWATCH_MASK __BIT(3)
-#define CPUWATCH_ASID __BIT(4)
-#define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE)
+#define CPUWATCH_WRITE __BIT(0)
+#define CPUWATCH_READ __BIT(1)
+#define CPUWATCH_EXEC __BIT(2)
+#define CPUWATCH_MASK __BIT(3)
+#define CPUWATCH_ASID __BIT(4)
+#define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE)
-#define CPUWATCH_MAX 8 /* max possible number of watchpoints */
+#define CPUWATCH_MAX 8 /* max possible number of watchpoints */
u_int cpuwatch_discover(void);
void cpuwatch_free(cpu_watchpoint_t *);
@@ -119,12 +119,12 @@ struct cpu_info {
u_int ci_pmap_asid_cur; /* current ASID */
struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
union pmap_segtab *ci_pmap_segtabs[2];
-#define ci_pmap_user_segtab ci_pmap_segtabs[0]
-#define ci_pmap_kern_segtab ci_pmap_segtabs[1]
+#define ci_pmap_user_segtab ci_pmap_segtabs[0]
+#define ci_pmap_kern_segtab ci_pmap_segtabs[1]
#ifdef _LP64
union pmap_segtab *ci_pmap_seg0tabs[2];
-#define ci_pmap_user_seg0tab ci_pmap_seg0tabs[0]
-#define ci_pmap_kern_seg0tab ci_pmap_seg0tabs[1]
+#define ci_pmap_user_seg0tab ci_pmap_seg0tabs[0]
+#define ci_pmap_kern_seg0tab ci_pmap_seg0tabs[1]
#endif
vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */
vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */
@@ -174,9 +174,9 @@ struct cpu_info {
/* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
// MIPS_CURLWP moved to <mips/regdef.h>
-#define MIPS_CURLWP_QUOTED "$24"
-#define MIPS_CURLWP_LABEL _L_T8
-#define MIPS_CURLWP_REG _R_T8
+#define MIPS_CURLWP_QUOTED "$24"
+#define MIPS_CURLWP_LABEL _L_T8
+#define MIPS_CURLWP_REG _R_T8
extern struct cpu_info cpu_info_store;
#ifdef MULTIPROCESSOR
@@ -279,10 +279,10 @@ void cpu_vmspace_exec(struct lwp *, vadd
/*
* CTL_MACHDEP definitions.
*/
-#define CPU_CONSDEV 1 /* dev_t: console terminal device */
-#define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
-#define CPU_ROOT_DEVICE 3 /* string: root device name */
-#define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */
-#define CPU_LMMI 5 /* Loongson multimedia instructions */
+#define CPU_CONSDEV 1 /* dev_t: console terminal device */
+#define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
+#define CPU_ROOT_DEVICE 3 /* string: root device name */
+#define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */
+#define CPU_LMMI 5 /* Loongson multimedia instructions */
#endif /* _CPU_H_ */
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.104 src/sys/arch/mips/include/cpuregs.h:1.105
--- src/sys/arch/mips/include/cpuregs.h:1.104 Sun Jul 26 07:52:07 2020
+++ src/sys/arch/mips/include/cpuregs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.104 2020/07/26 07:52:07 simonb Exp $ */
+/* $NetBSD: cpuregs.h,v 1.105 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -620,12 +620,12 @@
#define MIPS_COP_0_PWBASE _(5), 5
#define MIPS_COP_0_PWFIELD _(5), 6
#define MIPS_COP_0_PWSIZE _(5), 7
-#define MIPS_COP_0_PWCTL _(6), 6
-#define MIPS_COP_0_EIRR _(6), 6 /* RMI */
-#define MIPS_COP_0_EIMR _(6), 7 /* RMI */
+#define MIPS_COP_0_PWCTL _(6), 6
+#define MIPS_COP_0_EIRR _(6), 6 /* RMI */
+#define MIPS_COP_0_EIMR _(6), 7 /* RMI */
#define MIPS_COP_0_HWRENA _(7)
-#define MIPS_COP_0_BADINSTR _(8), 1
-#define MIPS_COP_0_BADINSTRP _(8), 2
+#define MIPS_COP_0_BADINSTR _(8), 1
+#define MIPS_COP_0_BADINSTRP _(8), 2
#define MIPS_COP_0_CVMCNT _(9), 6 /* CAVIUM */
#define MIPS_COP_0_CVMCTL _(9), 7 /* CAVIUM */
#define MIPS_COP_0_CVMMEMCTL _(11), 7 /* CAVIUM */
@@ -637,13 +637,13 @@
#define MIPS_COP_0_EBASE _(15), 1
#define MIPS_COP_0_CDMMBASE _(15), 2
#define MIPS_COP_0_CMGCRBASE _(15), 3
-#define MIPS_COP_0_CONFIG1 _(16), 1
-#define MIPS_COP_0_CONFIG2 _(16), 2
-#define MIPS_COP_0_CONFIG3 _(16), 3
-#define MIPS_COP_0_CONFIG4 _(16), 4
-#define MIPS_COP_0_CONFIG5 _(16), 5
-#define MIPS_COP_0_CONFIG6 _(16), 6
-#define MIPS_COP_0_CONFIG7 _(16), 7
+#define MIPS_COP_0_CONFIG1 _(16), 1
+#define MIPS_COP_0_CONFIG2 _(16), 2
+#define MIPS_COP_0_CONFIG3 _(16), 3
+#define MIPS_COP_0_CONFIG4 _(16), 4
+#define MIPS_COP_0_CONFIG5 _(16), 5
+#define MIPS_COP_0_CONFIG6 _(16), 6
+#define MIPS_COP_0_CONFIG7 _(16), 7
#define MIPS_COP_0_OSSCRATCH _(22) /* RMI */
#define MIPS_COP_0_DIAG _(22) /* LOONGSON2 */
#define MIPS_COP_0_MCD _(22) /* CAVIUM */
@@ -1133,22 +1133,22 @@
* The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
*/
-#define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL
+#define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL
-#define LOONGSON_AWR_BASE(master, window) \
+#define LOONGSON_AWR_BASE(master, window) \
(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00)
-#define LOONGSON_AWR_SIZE(master, window) \
+#define LOONGSON_AWR_SIZE(master, window) \
(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20)
-#define LOONGSON_AWR_MMAP(master, window) \
+#define LOONGSON_AWR_MMAP(master, window) \
(LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40)
/*
* Bits in the diagnostic register
*/
-#define COP_0_DIAG_ITLB_CLEAR 0x04
-#define COP_0_DIAG_BTB_CLEAR 0x02
-#define COP_0_DIAG_RAS_DISABLE 0x01
+#define COP_0_DIAG_ITLB_CLEAR 0x04
+#define COP_0_DIAG_BTB_CLEAR 0x02
+#define COP_0_DIAG_RAS_DISABLE 0x01
#endif /* MIPS3_LOONGSON2 */
Index: src/sys/arch/mips/include/db_machdep.h
diff -u src/sys/arch/mips/include/db_machdep.h:1.31 src/sys/arch/mips/include/db_machdep.h:1.32
--- src/sys/arch/mips/include/db_machdep.h:1.31 Mon Jul 13 05:20:45 2020
+++ src/sys/arch/mips/include/db_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.31 2020/07/13 05:20:45 simonb Exp $ */
+/* $NetBSD: db_machdep.h,v 1.32 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -58,25 +58,25 @@ extern db_regs_t ddb_regs; /* register s
#define PC_REGS(regs) ((regs)->r_regs[_R_PC])
-#define PC_ADVANCE(regs) do { \
+#define PC_ADVANCE(regs) do { \
if ((db_get_value((regs)->r_regs[_R_PC], sizeof(int), false) &\
0xfc00003f) == 0xd) \
(regs)->r_regs[_R_PC] += BKPT_SIZE; \
} while(0)
/* Similar to PC_ADVANCE(), except only advance on cpu_Debugger()'s bpt */
-#define PC_BREAK_ADVANCE(regs) do { \
+#define PC_BREAK_ADVANCE(regs) do { \
if (db_get_value((regs)->r_regs[_R_PC], sizeof(int), false) == 0xd) \
(regs)->r_regs[_R_PC] += BKPT_SIZE; \
} while(0)
#define BKPT_ADDR(addr) (addr) /* breakpoint address */
-#define BKPT_INST 0x0001000D
+#define BKPT_INST 0x0001000D
#define BKPT_SIZE (4) /* size of breakpoint inst */
#define BKPT_SET(inst, addr) (BKPT_INST)
#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAK)
-#define IS_WATCHPOINT_TRAP(type, code) (0) /* XXX mips3 watchpoint */
+#define IS_WATCHPOINT_TRAP(type, code) (0) /* XXX mips3 watchpoint */
/*
* Interface to disassembly (shared with mdb)
@@ -107,9 +107,9 @@ typedef mips_reg_t kgdb_reg_t;
/*
* MIPS cpus have no hardware single-step.
*/
-#define SOFTWARE_SSTEP
+#define SOFTWARE_SSTEP
-#define inst_trap_return(ins) ((ins)&0)
+#define inst_trap_return(ins) ((ins)&0)
bool inst_branch(int inst);
bool inst_call(int inst);
@@ -129,6 +129,6 @@ extern void (*cpu_reset_address)(void);
/*
* We have machine-dependent commands.
*/
-#define DB_MACHINE_COMMANDS
+#define DB_MACHINE_COMMANDS
#endif /* _MIPS_DB_MACHDEP_H_ */
Index: src/sys/arch/mips/include/ecoff_machdep.h
diff -u src/sys/arch/mips/include/ecoff_machdep.h:1.23 src/sys/arch/mips/include/ecoff_machdep.h:1.24
--- src/sys/arch/mips/include/ecoff_machdep.h:1.23 Thu Feb 23 18:56:12 2017
+++ src/sys/arch/mips/include/ecoff_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ecoff_machdep.h,v 1.23 2017/02/23 18:56:12 christos Exp $ */
+/* $NetBSD: ecoff_machdep.h,v 1.24 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone
@@ -34,46 +34,46 @@
* SUCH DAMAGE.
*/
-#define ECOFF_LDPGSZ 4096
+#define ECOFF_LDPGSZ 4096
-#define ECOFF_PAD
-#define ECOFF32_PAD
+#define ECOFF_PAD
+#define ECOFF32_PAD
-#define ECOFF32_MACHDEP \
+#define ECOFF32_MACHDEP \
ecoff32_ulong gprmask; \
ecoff32_ulong cprmask[4]; \
ecoff32_ulong gp_value
-#define ECOFF_MACHDEP \
+#define ECOFF_MACHDEP \
u_long gprmask; \
u_long cprmask[4]; \
u_long gp_value
#ifdef _KERNEL
#include <mips/locore.h> /* mips CPU architecture levels */
-#define _MIPS3_OK() CPUISMIPS3
+#define _MIPS3_OK() CPUISMIPS3
#else
-#define _MIPS3_OK() /*CONSTCOND*/1
+#define _MIPS3_OK() /*CONSTCOND*/1
#endif
-#define ECOFF_MAGIC_MIPSEB 0x0160 /* mips1, big-endian */
-#define ECOFF_MAGIC_MIPSEL 0x0162 /* mips1, little-endian */
-#define ECOFF_MAGIC_MIPSEL3 0x0142 /* mips3, little-endian */
+#define ECOFF_MAGIC_MIPSEB 0x0160 /* mips1, big-endian */
+#define ECOFF_MAGIC_MIPSEL 0x0162 /* mips1, little-endian */
+#define ECOFF_MAGIC_MIPSEL3 0x0142 /* mips3, little-endian */
#if BYTE_ORDER == LITTLE_ENDIAN
-#define ECOFF_BADMAG(ep) \
+#define ECOFF_BADMAG(ep) \
(! \
((ep)->f.f_magic == ECOFF_MAGIC_MIPSEL || \
(_MIPS3_OK() && (ep)->f.f_magic == ECOFF_MAGIC_MIPSEL3)) \
)
#endif
#if BYTE_ORDER == BIG_ENDIAN
-#define ECOFF_BADMAG(ep) ((ep)->f.f_magic != ECOFF_MAGIC_MIPSEB)
+#define ECOFF_BADMAG(ep) ((ep)->f.f_magic != ECOFF_MAGIC_MIPSEB)
#endif
-#define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
-#define ECOFF32_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
+#define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
+#define ECOFF32_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
#ifdef _KERNEL
struct proc;
@@ -143,7 +143,7 @@ struct ecoff_symhdr {
};
/* Macro for field name used by cgd's Alpha-derived code */
-#define esymMax iextMax
+#define esymMax iextMax
struct ecoff_extsym {
Index: src/sys/arch/mips/include/float.h
diff -u src/sys/arch/mips/include/float.h:1.17 src/sys/arch/mips/include/float.h:1.18
--- src/sys/arch/mips/include/float.h:1.17 Thu May 23 21:39:49 2013
+++ src/sys/arch/mips/include/float.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: float.h,v 1.17 2013/05/23 21:39:49 christos Exp $ */
+/* $NetBSD: float.h,v 1.18 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -26,7 +26,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MIPS_FLOAT_H_
-#define _MIPS_FLOAT_H_
+#define _MIPS_FLOAT_H_
#include <sys/cdefs.h>
@@ -34,7 +34,7 @@
#if __GNUC_PREREQ__(4,1)
-#define LDBL_MANT_DIG __LDBL_MANT_DIG__
+#define LDBL_MANT_DIG __LDBL_MANT_DIG__
#define LDBL_DIG __LDBL_DIG__
#define LDBL_MIN_EXP __LDBL_MIN_EXP__
#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
@@ -46,7 +46,7 @@
#else
-#define LDBL_MANT_DIG 113
+#define LDBL_MANT_DIG 113
#define LDBL_DIG 33
#define LDBL_MIN_EXP (-16381)
#define LDBL_MIN_10_EXP (-4931)
Index: src/sys/arch/mips/include/ptrace.h
diff -u src/sys/arch/mips/include/ptrace.h:1.17 src/sys/arch/mips/include/ptrace.h:1.18
--- src/sys/arch/mips/include/ptrace.h:1.17 Tue Jun 18 21:18:12 2019
+++ src/sys/arch/mips/include/ptrace.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.17 2019/06/18 21:18:12 kamil Exp $ */
+/* $NetBSD: ptrace.h,v 1.18 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -37,7 +37,7 @@
*/
#ifndef _MIPS_PTRACE_H_
-#define _MIPS_PTRACE_H_
+#define _MIPS_PTRACE_H_
/* MIPS PT_STEP PT_FIRSTMACH+0 might be defined by a port specific header */
#define PT_GETREGS (PT_FIRSTMACH + 1)
@@ -51,7 +51,7 @@
#define PT_CLEARSTEP (PT_FIRSTMACH + 6)
#endif
-#define PT_MACHDEP_STRINGS \
+#define PT_MACHDEP_STRINGS \
"PT_STEP", \
"PT_GETREGS", \
"PT_SETREGS", \
@@ -61,23 +61,23 @@
"PT_CLEARSTEP",
#include <machine/reg.h>
-#define PTRACE_REG_PC(r) (r)->r_regs[35]
-#define PTRACE_REG_FP(r) (r)->r_regs[30]
-#define PTRACE_REG_SET_PC(r, v) (r)->r_regs[35] = (v)
-#define PTRACE_REG_SP(r) (r)->r_regs[29]
-#define PTRACE_REG_INTRV(r) (r)->r_regs[2]
-
-#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x00, 0x00, 0x00, 0x0d })
-#define PTRACE_BREAKPOINT_ASM __asm __volatile("break")
-#define PTRACE_BREAKPOINT_SIZE 4
+#define PTRACE_REG_PC(r) (r)->r_regs[35]
+#define PTRACE_REG_FP(r) (r)->r_regs[30]
+#define PTRACE_REG_SET_PC(r, v) (r)->r_regs[35] = (v)
+#define PTRACE_REG_SP(r) (r)->r_regs[29]
+#define PTRACE_REG_INTRV(r) (r)->r_regs[2]
+
+#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x00, 0x00, 0x00, 0x0d })
+#define PTRACE_BREAKPOINT_ASM __asm __volatile("break")
+#define PTRACE_BREAKPOINT_SIZE 4
/*
* Glue for gdb: map NetBSD register names to legacy ptrace register names
*/
-#define GPR_BASE 0
+#define GPR_BASE 0
#ifndef JB_PC
-#define JB_PC 2 /* pc is at ((long *)jmp_buf)[2] */
+#define JB_PC 2 /* pc is at ((long *)jmp_buf)[2] */
#endif
#include <machine/reg.h> /* Historically in sys/ptrace.h */
Index: src/sys/arch/mips/include/int_fmtio.h
diff -u src/sys/arch/mips/include/int_fmtio.h:1.6 src/sys/arch/mips/include/int_fmtio.h:1.7
--- src/sys/arch/mips/include/int_fmtio.h:1.6 Wed Aug 13 19:48:17 2014
+++ src/sys/arch/mips/include/int_fmtio.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: int_fmtio.h,v 1.6 2014/08/13 19:48:17 matt Exp $ */
+/* $NetBSD: int_fmtio.h,v 1.7 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_INT_FMTIO_H_
-#define _MIPS_INT_FMTIO_H_
+#define _MIPS_INT_FMTIO_H_
#ifdef __INTPTR_FMTd__
#include <sys/common_int_fmtio.h>
Index: src/sys/arch/mips/include/int_mwgwtypes.h
diff -u src/sys/arch/mips/include/int_mwgwtypes.h:1.6 src/sys/arch/mips/include/int_mwgwtypes.h:1.7
--- src/sys/arch/mips/include/int_mwgwtypes.h:1.6 Wed Aug 13 22:25:39 2014
+++ src/sys/arch/mips/include/int_mwgwtypes.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: int_mwgwtypes.h,v 1.6 2014/08/13 22:25:39 matt Exp $ */
+/* $NetBSD: int_mwgwtypes.h,v 1.7 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _MIPS_INT_MWGWTYPES_H_
-#define _MIPS_INT_MWGWTYPES_H_
+#define _MIPS_INT_MWGWTYPES_H_
#ifdef __UINT_FAST64_TYPE__
#include <sys/common_int_mwgwtypes.h>
Index: src/sys/arch/mips/include/isa_machdep.h
diff -u src/sys/arch/mips/include/isa_machdep.h:1.8 src/sys/arch/mips/include/isa_machdep.h:1.9
--- src/sys/arch/mips/include/isa_machdep.h:1.8 Tue Oct 18 22:04:34 2016
+++ src/sys/arch/mips/include/isa_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: isa_machdep.h,v 1.8 2016/10/18 22:04:34 jdolecek Exp $ */
+/* $NetBSD: isa_machdep.h,v 1.9 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -135,9 +135,9 @@ struct mips_isa_chipset {
_isa_dmamem_unmap(&(ic)->ic_dmastate, (c), (k), (s))
#define isa_dmamem_mmap(ic, c, a, s, o, p, f) \
_isa_dmamem_mmap(&(ic)->ic_dmastate, (c), (a), (s), (o), (p), (f))
-#define isa_drq_alloc(ic, c) \
+#define isa_drq_alloc(ic, c) \
_isa_drq_alloc(&(ic)->ic_dmastate, c)
-#define isa_drq_free(ic, c) \
+#define isa_drq_free(ic, c) \
_isa_drq_free(&(ic)->ic_dmastate, c)
#define isa_drq_isfree(ic, c) \
_isa_drq_isfree(&(ic)->ic_dmastate, (c))
@@ -151,7 +151,7 @@ struct mips_isa_chipset {
/*
* mips-specific ISA functions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
- */
+ */
#define isa_intr_string(c, i, buf, len) \
(*(c)->ic_intr_string)((c)->ic_v, (i), buf, len)
Index: src/sys/arch/mips/include/kdbparam.h
diff -u src/sys/arch/mips/include/kdbparam.h:1.8 src/sys/arch/mips/include/kdbparam.h:1.9
--- src/sys/arch/mips/include/kdbparam.h:1.8 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/include/kdbparam.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: kdbparam.h,v 1.8 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: kdbparam.h,v 1.9 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -39,14 +39,14 @@
*/
#if BYTE_ORDER == LITTLE_ENDIAN
-#define kdbshorten(w) ((w) & 0xFFFF)
+#define kdbshorten(w) ((w) & 0xFFFF)
#define kdbbyte(w) ((w) & 0xFF)
#define kdbitol(a,b) ((long)(((b) << 16) | ((a) & 0xFFFF)))
#define kdbbtol(a) ((long)(a))
#endif
-#define LPRMODE "%R"
-#define OFFMODE "+%R"
+#define LPRMODE "%R"
+#define OFFMODE "+%R"
#define SETBP(ins) MIPS_BREAK_BRKPT
Index: src/sys/arch/mips/include/mipsNN.h
diff -u src/sys/arch/mips/include/mipsNN.h:1.8 src/sys/arch/mips/include/mipsNN.h:1.9
--- src/sys/arch/mips/include/mipsNN.h:1.8 Sat Jun 13 14:41:24 2020
+++ src/sys/arch/mips/include/mipsNN.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsNN.h,v 1.8 2020/06/13 14:41:24 simonb Exp $ */
+/* $NetBSD: mipsNN.h,v 1.9 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright 2000, 2001
@@ -153,10 +153,10 @@
#define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x))
/* "C2" (R): Coprocessor 2 implemented if set. */
-#define MIPSNN_CFG1_C2 0x00000040
+#define MIPSNN_CFG1_C2 0x00000040
/* "MD" (R): MDMX ASE implemented if set. */
-#define MIPSNN_CFG1_MD 0x00000020
+#define MIPSNN_CFG1_MD 0x00000020
/* "PC" (R): Performance Counters implemented if set. */
#define MIPSNN_CFG1_PC 0x00000010
@@ -304,27 +304,27 @@
*/
/* "CTLB_SIZE" (R): Number of Combined TLB entries - 1. */
-#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_MASK 0xffff0000
-#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_SHIFT 16
+#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_MASK 0xffff0000
+#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_SHIFT 16
/* "VTLB_SIZE" (R): Number of Variable TLB entries - 1. */
-#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_MASK 0x0000ffc0
-#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_SHIFT 6
+#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_MASK 0x0000ffc0
+#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_SHIFT 6
/* "ELVT" (RW): Enable Large Variable TLB. */
-#define MIPSNN_RMIXLP_CFG6_ELVT 0x00000020
+#define MIPSNN_RMIXLP_CFG6_ELVT 0x00000020
/* "EPW" (RW): Enable PageWalker. */
-#define MIPSNN_RMIXLP_CFG6_EPW 0x00000008
+#define MIPSNN_RMIXLP_CFG6_EPW 0x00000008
/* "EFT" (RW): Enable Fixed TLB. */
-#define MIPSNN_RMIXLP_CFG6_EFT 0x00000004
+#define MIPSNN_RMIXLP_CFG6_EFT 0x00000004
/* "PWI" (R): PageWalker implemented. */
-#define MIPSNN_RMIXLP_CFG6_PWI 0x00000001
+#define MIPSNN_RMIXLP_CFG6_PWI 0x00000001
/* "FTI" (R): Fixed TLB implemented. */
-#define MIPSNN_RMIXLP_CFG6_FTI 0x00000001
+#define MIPSNN_RMIXLP_CFG6_FTI 0x00000001
/*
* Values in Configuration Register 7 (CP0 Register 16, Select 7)
@@ -332,11 +332,11 @@
*/
/* "LG" (RW): Small or Large Page. */
-#define MIPSNN_RMIXLP_CFG7_LG_MASK __BIT(61)
+#define MIPSNN_RMIXLP_CFG7_LG_MASK __BIT(61)
/* "MASKLG" (RW): large page size supported in CAM only. */
-#define MIPSNN_RMIXLP_CFG7_MASKLG_MASK 0x0000ff00
-#define MIPSNN_RMIXLP_CFG7_MASKLG_SHIFT 8
+#define MIPSNN_RMIXLP_CFG7_MASKLG_MASK 0x0000ff00
+#define MIPSNN_RMIXLP_CFG7_MASKLG_SHIFT 8
#define MIPSNN_RMIXLP_CFG7_MASKLG_4KB (0xff >> 8)
#define MIPSNN_RMIXLP_CFG7_MASKLG_16KB (0xff >> 7)
@@ -349,8 +349,8 @@
#define MIPSNN_RMIXLP_CFG7_MASKLG_256MB (0xff >> 0)
/* "MASKSM" (RW): small page size supported in CAM/RAM. */
-#define MIPSNN_RMIXLP_CFG7_MASKSM_MASK 0x000000ff
-#define MIPSNN_RMIXLP_CFG7_MASKSM_SHIFT 0
+#define MIPSNN_RMIXLP_CFG7_MASKSM_MASK 0x000000ff
+#define MIPSNN_RMIXLP_CFG7_MASKSM_SHIFT 0
#define MIPSNN_RMIXLP_CFG7_MASKSM_4KB (0xff >> 8)
#define MIPSNN_RMIXLP_CFG7_MASKSM_16KB (0xff >> 7)
@@ -367,33 +367,33 @@
* for the MTI 74K and 1074K cores.
*/
/* "SPCD" (R/W): Sleep state Perforance Counter Disable. */
-#define MIPSNN_MTI_CFG6_SPCD __BIT(14)
+#define MIPSNN_MTI_CFG6_SPCD __BIT(14)
/* "SYND" (R/W): SYNonym tag update Disable. */
-#define MIPSNN_MTI_CFG6_SYND __BIT(13)
+#define MIPSNN_MTI_CFG6_SYND __BIT(13)
/* "IFUPerfCtl" (R/W): IFU Performance Control. */
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_MASK __BIT(12:10)
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALL 0
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_JUMP 1
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALLED_INSN 2
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_MISPREDICTION 3
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_PREDICTION 4
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_BAD_JR_CACHE_ENTRY 5
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_UNIMPL 6
-#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CBRACH_TAKEN 7
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_MASK __BIT(12:10)
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALL 0
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_JUMP 1
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALLED_INSN 2
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_MISPREDICTION 3
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_PREDICTION 4
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_BAD_JR_CACHE_ENTRY 5
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_UNIMPL 6
+#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CBRACH_TAKEN 7
/* "NMRUP" (R): Most Recently Used JTLB Replacement scheme Present. */
-#define MIPSNN_MTI_CFG6_NMRUP __BIT(9) /* 1: implemented */
+#define MIPSNN_MTI_CFG6_NMRUP __BIT(9) /* 1: implemented */
/* "NMRUD" (R/W): NMRU Disable. */
-#define MIPSNN_MTI_CFG6_NMRUD __BIT(8) /* 1: TLBWR is random */
+#define MIPSNN_MTI_CFG6_NMRUD __BIT(8) /* 1: TLBWR is random */
/* "JRCP" (R): JR Cache Present. */
-#define MIPSNN_MTI_CFG6_JRCP __BIT(1) /* 1: implemented */
+#define MIPSNN_MTI_CFG6_JRCP __BIT(1) /* 1: implemented */
/* "JRCD" (R/W): JR Cache prediction Disable. */
-#define MIPSNN_MTI_CFG6_JRCD __BIT(0) /* 1: disabled */
+#define MIPSNN_MTI_CFG6_JRCD __BIT(0) /* 1: disabled */
/*
@@ -402,52 +402,52 @@
*/
/* "WII" (R): Wait IE Ignore. */
-#define MIPSNN_MTI_CFG7_WII __BIT(31)
+#define MIPSNN_MTI_CFG7_WII __BIT(31)
/* "FPFS" (R/W): Fast Prepare For Store (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_FPFS __BIT(30)
+#define MIPSNN_MTI_CFG7_FPFS __BIT(30)
/* "IHB" (R/W): Implicit HB (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_IHB __BIT(29)
+#define MIPSNN_MTI_CFG7_IHB __BIT(29)
/* "FPR1" (R): Float Point Ratio 1 (74K, 1074K). */
-#define MIPSNN_MTI_CFG7_FPR1 __BIT(28) /* 1: 3:2 */
+#define MIPSNN_MTI_CFG7_FPR1 __BIT(28) /* 1: 3:2 */
/* "SEHB" (R/W): slow EHB (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_SEHB __BIT(27)
+#define MIPSNN_MTI_CFG7_SEHB __BIT(27)
/* "CP2IO" (R/W): Force COP2 data to be in-order (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_CP2IO __BIT(26)
+#define MIPSNN_MTI_CFG7_CP2IO __BIT(26)
/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
+#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
+#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
/* "IALU" (R/W): Issue ALU-side instructions in program order (74K, 1074K) */
-#define MIPSNN_MTI_CFG7_IALU __BIT(24)
+#define MIPSNN_MTI_CFG7_IALU __BIT(24)
/* "DGHR" (R/W): disable global history in branch prediction (74K, 1074K). */
-#define MIPSNN_MTI_CFG7_DGHR __BIT(23) /* 1: disable */
+#define MIPSNN_MTI_CFG7_DGHR __BIT(23) /* 1: disable */
/* "SG" (R/W): Single Graduation per cycle (74K, 1074K). */
-#define MIPSNN_MTI_CFG7_SG __BIT(22) /* 1: no superscalar */
+#define MIPSNN_MTI_CFG7_SG __BIT(22) /* 1: no superscalar */
/* "SUI" (R/W): Strict Uncached Instruction (SUI) policy control (74K, 1074K). */
-#define MIPSNN_MTI_CFG7_SUI __BIT(21)
+#define MIPSNN_MTI_CFG7_SUI __BIT(21)
/* "NCWB" (R/W): Non-Choerent WriteBack (1004K). */
-#define MIPSNN_MTI_CFG7_NCWB __BIT(20)
+#define MIPSNN_MTI_CFG7_NCWB __BIT(20)
/* "PCT" (R): Performance Counters per TC (34K, 1004K). */
-#define MIPSNN_MTI_CFG7_PCT __BIT(19)
+#define MIPSNN_MTI_CFG7_PCT __BIT(19)
/* "HCI" (R): Hardware Cache Initialization. */
-#define MIPSNN_MTI_CFG7_HCI __BIT(18)
+#define MIPSNN_MTI_CFG7_HCI __BIT(18)
/* "FPR" (R): Float Point Ratio. */
-#define MIPSNN_MTI_CFG7_FPR0 __BIT(17) /* 1: half speed */
+#define MIPSNN_MTI_CFG7_FPR0 __BIT(17) /* 1: half speed */
#define MIPSNN_MTI_CFG7_FPR_MASK (MIPSNN_MTI_CFG7_FPR1|MIPSNN_MTI_CFG7_FPR0)
#define MIPSNN_MTI_CFG7_FPR_SHIFT 0
@@ -457,10 +457,10 @@
#define MIPSNN_MTI_CFG7_FPR_RESERVED MIPSNN_MTI_CFG7_FPR_MASK
/* "AR" (R): Alias Removal. */
-#define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */
+#define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */
/* "PREF" (R/W): Instruction Prefetching (74K, 1074K). */
-#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12:11)
+#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12:11)
#define MIPSNN_MTI_CFG7_PREF_SHIFT 11
#define MIPSNN_MTI_CFG7_PREF_DISABLE 0
#define MIPSNN_MTI_CFG7_PREF_ONELINE 1
@@ -468,34 +468,34 @@
#define MIPSNN_MTI_CFG7_PREF_TWOLINES 3
/* "IAR" (R): Instruction Alias Removal. */
-#define MIPSNN_MTI_CFG7_IAR __BIT(10) /* 1: no virt aliases */
+#define MIPSNN_MTI_CFG7_IAR __BIT(10) /* 1: no virt aliases */
/* "IVA" (R or RW): Instruction Virtual Alias fix disable. */
-#define MIPSNN_MTI_CFG7_IVA __BIT(9) /* 1: fix disable */
+#define MIPSNN_MTI_CFG7_IVA __BIT(9) /* 1: fix disable */
/* "ES" (RW): External Sync. */
-#define MIPSNN_MTI_CFG7_ES __BIT(8)
+#define MIPSNN_MTI_CFG7_ES __BIT(8)
/* "BTLM" (RW): Block TC on Load Miss. */
-#define MIPSNN_MTI_CFG7_BTLM __BIT(7)
+#define MIPSNN_MTI_CFG7_BTLM __BIT(7)
/* "CPOOO" (RW): Out-Of-Order on Coprocessor interfaces (COP0/COP1). */
-#define MIPSNN_MTI_CFG7_CPOOO __BIT(6) /* 1: disable OOO */
+#define MIPSNN_MTI_CFG7_CPOOO __BIT(6) /* 1: disable OOO */
/* "NBLSU" (RW): Non-Blocking LSU. (24K, 34K) */
-#define MIPSNN_MTI_CFG7_NBLSU __BIT(5) /* 1: stalls pipeline */
+#define MIPSNN_MTI_CFG7_NBLSU __BIT(5) /* 1: stalls pipeline */
/* "UBL" (RW): Uncached Loads Blocking. */
-#define MIPSNN_MTI_CFG7_UBL __BIT(4) /* 1: blocking loads */
+#define MIPSNN_MTI_CFG7_UBL __BIT(4) /* 1: blocking loads */
/* "BP" (RW): Branch Prediction. */
-#define MIPSNN_MTI_CFG7_BP __BIT(3) /* 1: disabled */
+#define MIPSNN_MTI_CFG7_BP __BIT(3) /* 1: disabled */
/* "RPS" (RW): Return Prediction Stack. */
-#define MIPSNN_MTI_CFG7_RPS __BIT(2) /* 1: disabled */
+#define MIPSNN_MTI_CFG7_RPS __BIT(2) /* 1: disabled */
/* "BHT" (RW): Branch History Table. */
-#define MIPSNN_MTI_CFG7_BHT __BIT(1) /* 1: disabled */
+#define MIPSNN_MTI_CFG7_BHT __BIT(1) /* 1: disabled */
/* "SL" (RW): Scheduled Loads. */
-#define MIPSNN_MTI_CFG7_SL __BIT(0) /* 1: load misses block */
+#define MIPSNN_MTI_CFG7_SL __BIT(0) /* 1: load misses block */
Index: src/sys/arch/mips/include/pci_machdep.h
diff -u src/sys/arch/mips/include/pci_machdep.h:1.8 src/sys/arch/mips/include/pci_machdep.h:1.9
--- src/sys/arch/mips/include/pci_machdep.h:1.8 Sat Mar 29 19:28:29 2014
+++ src/sys/arch/mips/include/pci_machdep.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.h,v 1.8 2014/03/29 19:28:29 christos Exp $ */
+/* $NetBSD: pci_machdep.h,v 1.9 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -28,7 +28,7 @@
*/
#ifndef _MIPS_INCLUDE_PCI_MACHDEP_H_
-#define _MIPS_INCLUDE_PCI_MACHDEP_H_
+#define _MIPS_INCLUDE_PCI_MACHDEP_H_
/*
* __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH (if used) needs to be
@@ -63,7 +63,7 @@ struct mips_pci_chipset {
void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
void *pc_intr_v;
- int (*pc_intr_map)(const struct pci_attach_args *,
+ int (*pc_intr_map)(const struct pci_attach_args *,
pci_intr_handle_t *);
const char *(*pc_intr_string)(void *, pci_intr_handle_t,
char *, size_t);
Index: src/sys/arch/mips/include/limits.h
diff -u src/sys/arch/mips/include/limits.h:1.27 src/sys/arch/mips/include/limits.h:1.28
--- src/sys/arch/mips/include/limits.h:1.27 Mon Jan 21 20:28:18 2019
+++ src/sys/arch/mips/include/limits.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: limits.h,v 1.27 2019/01/21 20:28:18 dholland Exp $ */
+/* $NetBSD: limits.h,v 1.28 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988, 1993
@@ -112,19 +112,19 @@
#if defined(_XOPEN_SOURCE) || defined(_NETBSD_SOURCE)
#ifdef _LP64
-#define LONG_BIT 64
+#define LONG_BIT 64
#else
-#define LONG_BIT 32
+#define LONG_BIT 32
#endif
-#define WORD_BIT 32
+#define WORD_BIT 32
-#define DBL_DIG __DBL_DIG__
-#define DBL_MAX __DBL_MAX__
-#define DBL_MIN __DBL_MIN__
+#define DBL_DIG __DBL_DIG__
+#define DBL_MAX __DBL_MAX__
+#define DBL_MIN __DBL_MIN__
-#define FLT_DIG __FLT_DIG__
-#define FLT_MAX __FLT_MAX__
-#define FLT_MIN __FLT_MIN__
+#define FLT_DIG __FLT_DIG__
+#define FLT_MAX __FLT_MAX__
+#define FLT_MIN __FLT_MIN__
#endif
#endif /* _MIPS_LIMITS_H_ */
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.109 src/sys/arch/mips/include/locore.h:1.110
--- src/sys/arch/mips/include/locore.h:1.109 Thu Jul 23 19:22:13 2020
+++ src/sys/arch/mips/include/locore.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.109 2020/07/23 19:22:13 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.110 2020/07/26 08:08:41 simonb Exp $ */
/*
* This file should not be included by MI code!!!
@@ -26,7 +26,7 @@
*/
#ifndef _MIPS_LOCORE_H
-#define _MIPS_LOCORE_H
+#define _MIPS_LOCORE_H
#if defined(_KERNEL_OPT)
#include "opt_cputype.h"
@@ -41,9 +41,9 @@
#include <mips/reg.h>
#ifndef __BSD_PTENTRY_T__
-#define __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
typedef uint32_t pt_entry_t;
-#define PRIxPTE PRIx32
+#define PRIxPTE PRIx32
#endif
#include <uvm/pmap/tlb.h>
@@ -77,13 +77,13 @@ typedef uint32_t pt_entry_t;
#define MIPS3_PLUS 1
#if !defined(MIPS32) && !defined(MIPS32R2)
-#define MIPS3_64BIT 1
+#define MIPS3_64BIT 1
#endif
#if !defined(MIPS3) && !defined(MIPS4)
-#define MIPSNN 1
+#define MIPSNN 1
#endif
#if defined(MIPS32R2) || defined(MIPS64R2)
-#define MIPSNNR2 1
+#define MIPSNNR2 1
#endif
#else
#undef MIPS3_PLUS
@@ -298,13 +298,13 @@ struct mips_options {
#else
#define MIPS_HAS_R4K_MMU 1
#if !defined(MIPS3_4100)
-#define MIPS_HAS_LLSC 1
+#define MIPS_HAS_LLSC 1
#else
-#define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
+#define MIPS_HAS_LLSC (mips_options.mips_has_llsc)
#endif
#endif
#define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
-#define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
+#define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
# define MIPS_HAS_USERLOCAL (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
/* This test is ... rather bogus */
@@ -726,33 +726,33 @@ void mips_page_physload(vaddr_t, vaddr_t
/*
* CPU identification, from PRID register.
*/
-#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
-#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
+#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
+#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
/* pre-MIPS32/64 */
-#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
-#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
-#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
+#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
+#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
+#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
/* MIPS32/64 */
-#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
-#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
-#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
-#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
-#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
-#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
-#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
-#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
-#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
-#define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */
-#define MIPS_PRID_CID_LSI 0x08 /* LSI */
+#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
+#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
+#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
+#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
+#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
+#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
+#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
+#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
+#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
+#define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */
+#define MIPS_PRID_CID_LSI 0x08 /* LSI */
/* 0x09 unannounced */
/* 0x0a unannounced */
-#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
-#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */
-#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
-#define MIPS_PRID_CID_INGENIC 0xe1
-#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
+#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
+#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */
+#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
+#define MIPS_PRID_CID_INGENIC 0xe1
+#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
#ifdef _KERNEL
/*
@@ -771,43 +771,43 @@ void mips_machdep_cache_config(void);
*/
#if 0
-#define TF_AST 0 /* really zero */
-#define TF_V0 _R_V0
-#define TF_V1 _R_V1
-#define TF_A0 _R_A0
-#define TF_A1 _R_A1
-#define TF_A2 _R_A2
-#define TF_A3 _R_A3
-#define TF_T0 _R_T0
-#define TF_T1 _R_T1
-#define TF_T2 _R_T2
-#define TF_T3 _R_T3
+#define TF_AST 0 /* really zero */
+#define TF_V0 _R_V0
+#define TF_V1 _R_V1
+#define TF_A0 _R_A0
+#define TF_A1 _R_A1
+#define TF_A2 _R_A2
+#define TF_A3 _R_A3
+#define TF_T0 _R_T0
+#define TF_T1 _R_T1
+#define TF_T2 _R_T2
+#define TF_T3 _R_T3
#if defined(__mips_n32) || defined(__mips_n64)
-#define TF_A4 _R_A4
-#define TF_A5 _R_A5
-#define TF_A6 _R_A6
-#define TF_A7 _R_A7
-#else
-#define TF_T4 _R_T4
-#define TF_T5 _R_T5
-#define TF_T6 _R_T6
-#define TF_T7 _R_T7
+#define TF_A4 _R_A4
+#define TF_A5 _R_A5
+#define TF_A6 _R_A6
+#define TF_A7 _R_A7
+#else
+#define TF_T4 _R_T4
+#define TF_T5 _R_T5
+#define TF_T6 _R_T6
+#define TF_T7 _R_T7
#endif /* __mips_n32 || __mips_n64 */
-#define TF_TA0 _R_TA0
-#define TF_TA1 _R_TA1
-#define TF_TA2 _R_TA2
-#define TF_TA3 _R_TA3
-
-#define TF_T8 _R_T8
-#define TF_T9 _R_T9
-
-#define TF_RA _R_RA
-#define TF_SR _R_SR
-#define TF_MULLO _R_MULLO
-#define TF_MULHI _R_MULLO
-#define TF_EPC _R_PC /* may be changed by trap() call */
+#define TF_TA0 _R_TA0
+#define TF_TA1 _R_TA1
+#define TF_TA2 _R_TA2
+#define TF_TA3 _R_TA3
+
+#define TF_T8 _R_T8
+#define TF_T9 _R_T9
+
+#define TF_RA _R_RA
+#define TF_SR _R_SR
+#define TF_MULLO _R_MULLO
+#define TF_MULHI _R_MULLO
+#define TF_EPC _R_PC /* may be changed by trap() call */
#define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t))
#endif
@@ -864,20 +864,20 @@ struct pridtab {
/*
* bitfield defines for cpu_cp0flags
*/
-#define MIPS_CP0FL_USE __BIT(0) /* use these flags */
-#define MIPS_CP0FL_ECC __BIT(1)
-#define MIPS_CP0FL_CACHE_ERR __BIT(2)
-#define MIPS_CP0FL_EIRR __BIT(3)
-#define MIPS_CP0FL_EIMR __BIT(4)
-#define MIPS_CP0FL_EBASE __BIT(5) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG __BIT(6) /* XXX defined - doesn't need to be hard coded */
-#define MIPS_CP0FL_CONFIG1 __BIT(7) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG2 __BIT(8) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG3 __BIT(9) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG4 __BIT(10) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG5 __BIT(11) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG6 __BIT(12) /* XXX probeable - shouldn't be hard coded */
-#define MIPS_CP0FL_CONFIG7 __BIT(13) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_USE __BIT(0) /* use these flags */
+#define MIPS_CP0FL_ECC __BIT(1)
+#define MIPS_CP0FL_CACHE_ERR __BIT(2)
+#define MIPS_CP0FL_EIRR __BIT(3)
+#define MIPS_CP0FL_EIMR __BIT(4)
+#define MIPS_CP0FL_EBASE __BIT(5) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG __BIT(6) /* XXX defined - doesn't need to be hard coded */
+#define MIPS_CP0FL_CONFIG1 __BIT(7) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG2 __BIT(8) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG3 __BIT(9) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG4 __BIT(10) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG5 __BIT(11) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG6 __BIT(12) /* XXX probeable - shouldn't be hard coded */
+#define MIPS_CP0FL_CONFIG7 __BIT(13) /* XXX probeable - shouldn't be hard coded */
/*
* cpu_cidflags defines, by company
@@ -885,13 +885,13 @@ struct pridtab {
/*
* RMI company-specific cpu_cidflags
*/
-#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
+#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
# define CIDFL_RMI_TYPE_XLR 0
# define CIDFL_RMI_TYPE_XLS 1
# define CIDFL_RMI_TYPE_XLP 2
-#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)
+#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)
# define MIPS_CIDFL_RMI_THREADS_SHIFT 3
-#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)
+#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)
# define MIPS_CIDFL_RMI_CORES_SHIFT 7
# define LOG2_1 0
# define LOG2_2 1
@@ -906,7 +906,7 @@ struct pridtab {
# define MIPS_CIDFL_RMI_NCORES(cidfl) \
(1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \
>> MIPS_CIDFL_RMI_CORES_SHIFT))
-#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11)
+#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11)
# define MIPS_CIDFL_RMI_L2SZ_SHIFT 11
# define RMI_L2SZ_256KB 0
# define RMI_L2SZ_512KB 1
Index: src/sys/arch/mips/include/math.h
diff -u src/sys/arch/mips/include/math.h:1.7 src/sys/arch/mips/include/math.h:1.8
--- src/sys/arch/mips/include/math.h:1.7 Fri Jan 31 19:38:06 2014
+++ src/sys/arch/mips/include/math.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: math.h,v 1.7 2014/01/31 19:38:06 matt Exp $ */
+/* $NetBSD: math.h,v 1.8 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -27,5 +27,5 @@
*/
#define __HAVE_NANF
#if defined(__mips_n32) || defined(__mips_n64)
-#define __HAVE_LONG_DOUBLE 128
+#define __HAVE_LONG_DOUBLE 128
#endif
Index: src/sys/arch/mips/include/r3900regs.h
diff -u src/sys/arch/mips/include/r3900regs.h:1.7 src/sys/arch/mips/include/r3900regs.h:1.8
--- src/sys/arch/mips/include/r3900regs.h:1.7 Mon Apr 28 20:23:28 2008
+++ src/sys/arch/mips/include/r3900regs.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: r3900regs.h,v 1.7 2008/04/28 20:23:28 martin Exp $ */
+/* $NetBSD: r3900regs.h,v 1.8 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -42,13 +42,13 @@
*/
#define R3900_CR_EXC_CODE MIPS3_CR_EXC_CODE /* five bits */
#undef MIPS1_CR_EXC_CODE
-#define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE
+#define MIPS1_CR_EXC_CODE R3900_CR_EXC_CODE
/*
* [status register]
* R3900 don't have PE, CM, PZ, SwC and IsC.
*/
-#define R3900_SR_NMI 0x00100000 /* r3k PE position */
+#define R3900_SR_NMI 0x00100000 /* r3k PE position */
#if 0
#undef MIPS1_PARITY_ERR
#undef MIPS1_CACHE_MISS
@@ -70,10 +70,10 @@
#define R3900_COP_0_DEBUG $16
#define R3900_COP_0_DEPC $17
-#define R3920_COP_0_PAGEMASK $5
-#define R3920_COP_0_WIRED $6
+#define R3920_COP_0_PAGEMASK $5
+#define R3920_COP_0_WIRED $6
#define R3920_COP_0_CACHE $7
-#define R3920_COP_0_TAG_LO $20
+#define R3920_COP_0_TAG_LO $20
/*
* TLB entry
@@ -84,68 +84,68 @@
/*
* Config register (R3900 specific)
*/
-#define R3900_CONFIG_ICS_SHIFT 19
-#define R3900_CONFIG_ICS_MASK 0x00380000
-#define R3900_CONFIG_ICS_1KB 0x00000000
-#define R3900_CONFIG_ICS_2KB 0x00080000
-#define R3900_CONFIG_ICS_4KB 0x00100000
-#define R3900_CONFIG_ICS_8KB 0x00180000
-#define R3900_CONFIG_ICS_16KB 0x00200000
-
-#define R3900_CONFIG_DCS_SHIFT 16
-#define R3900_CONFIG_DCS_1KB 0x00000000
-#define R3900_CONFIG_DCS_2KB 0x00010000
-#define R3900_CONFIG_DCS_4KB 0x00020000
-#define R3900_CONFIG_DCS_8KB 0x00030000
-#define R3900_CONFIG_DCS_16KB 0x00040000
-
-#define R3900_CONFIG_DCS_MASK 0x00070000
-#define R3900_CONFIG_CWFON 0x00004000
-#define R3900_CONFIG_WBON 0x00002000
-#define R3900_CONFIG_RF_SHIFT 10
-#define R3900_CONFIG_RF_MASK 0x00000c00
-#define R3900_CONFIG_DOZE 0x00000200
-#define R3900_CONFIG_HALT 0x00000100
-#define R3900_CONFIG_LOCK 0x00000080
-#define R3900_CONFIG_ICE 0x00000020
-#define R3900_CONFIG_DCE 0x00000010
-#define R3900_CONFIG_IRSIZE_SHIFT 2
-#define R3900_CONFIG_IRSIZE_MASK 0x0000000c
-#define R3900_CONFIG_DRSIZE_SHIFT 0
-#define R3900_CONFIG_DRSIZE_MASK 0x00000003
+#define R3900_CONFIG_ICS_SHIFT 19
+#define R3900_CONFIG_ICS_MASK 0x00380000
+#define R3900_CONFIG_ICS_1KB 0x00000000
+#define R3900_CONFIG_ICS_2KB 0x00080000
+#define R3900_CONFIG_ICS_4KB 0x00100000
+#define R3900_CONFIG_ICS_8KB 0x00180000
+#define R3900_CONFIG_ICS_16KB 0x00200000
+
+#define R3900_CONFIG_DCS_SHIFT 16
+#define R3900_CONFIG_DCS_1KB 0x00000000
+#define R3900_CONFIG_DCS_2KB 0x00010000
+#define R3900_CONFIG_DCS_4KB 0x00020000
+#define R3900_CONFIG_DCS_8KB 0x00030000
+#define R3900_CONFIG_DCS_16KB 0x00040000
+
+#define R3900_CONFIG_DCS_MASK 0x00070000
+#define R3900_CONFIG_CWFON 0x00004000
+#define R3900_CONFIG_WBON 0x00002000
+#define R3900_CONFIG_RF_SHIFT 10
+#define R3900_CONFIG_RF_MASK 0x00000c00
+#define R3900_CONFIG_DOZE 0x00000200
+#define R3900_CONFIG_HALT 0x00000100
+#define R3900_CONFIG_LOCK 0x00000080
+#define R3900_CONFIG_ICE 0x00000020
+#define R3900_CONFIG_DCE 0x00000010
+#define R3900_CONFIG_IRSIZE_SHIFT 2
+#define R3900_CONFIG_IRSIZE_MASK 0x0000000c
+#define R3900_CONFIG_DRSIZE_SHIFT 0
+#define R3900_CONFIG_DRSIZE_MASK 0x00000003
/*
* CACHE
*/
/* Cache size (limit) */
/* R3900/R3920 */
-#define R3900_C_SIZE_MIN 1024
-#define R3900_C_SIZE_MAX 8192
+#define R3900_C_SIZE_MIN 1024
+#define R3900_C_SIZE_MAX 8192
/* Cache line size */
/* R3900 */
-#define R3900_C_LSIZE_I 16
-#define R3900_C_LSIZE_D 4
+#define R3900_C_LSIZE_I 16
+#define R3900_C_LSIZE_D 4
/* R3920 */
-#define R3920_C_LSIZE_I 16
-#define R3920_C_LSIZE_D 16
+#define R3920_C_LSIZE_I 16
+#define R3920_C_LSIZE_D 16
/* Cache operation */
/* R3900 */
-#define R3900_C_IINV_I 0x00
-#define R3900_C_IWBINV_D 0x01
-#define R3900_C_ILRUC_I 0x04
-#define R3900_C_ILRUC_D 0x05
-#define R3900_C_ILCKC_D 0x09 /* R3900 only */
-#define R3900_C_HINV_D 0x11
+#define R3900_C_IINV_I 0x00
+#define R3900_C_IWBINV_D 0x01
+#define R3900_C_ILRUC_I 0x04
+#define R3900_C_ILRUC_D 0x05
+#define R3900_C_ILCKC_D 0x09 /* R3900 only */
+#define R3900_C_HINV_D 0x11
/* R3920 */
-#define R3920_C_IINV_I 0x00
-#define R3920_C_IWBINV_D 0x01
-#define R3920_C_ILRUC_I 0x04
-#define R3920_C_ILRUC_D 0x05
-#define R3920_C_ILDTAG_I 0x0c /* R3920 only */
-#define R3920_C_ILDTAG_D 0x0d /* R3920 only */
-#define R3920_C_HINV_I 0x10 /* R3920 only */
-#define R3920_C_HINV_D 0x11
-#define R3920_C_HWBINV_D 0x14 /* R3920 only */
-#define R3920_C_HWB_D 0x18 /* R3920 only */
-#define R3920_C_ISTTAG_I 0x1c /* R3920 only */
-#define R3920_C_ISTTAG_D 0x1d /* R3920 only */
+#define R3920_C_IINV_I 0x00
+#define R3920_C_IWBINV_D 0x01
+#define R3920_C_ILRUC_I 0x04
+#define R3920_C_ILRUC_D 0x05
+#define R3920_C_ILDTAG_I 0x0c /* R3920 only */
+#define R3920_C_ILDTAG_D 0x0d /* R3920 only */
+#define R3920_C_HINV_I 0x10 /* R3920 only */
+#define R3920_C_HINV_D 0x11
+#define R3920_C_HWBINV_D 0x14 /* R3920 only */
+#define R3920_C_HWB_D 0x18 /* R3920 only */
+#define R3920_C_ISTTAG_I 0x1c /* R3920 only */
+#define R3920_C_ISTTAG_D 0x1d /* R3920 only */
Index: src/sys/arch/mips/include/mcontext.h
diff -u src/sys/arch/mips/include/mcontext.h:1.22 src/sys/arch/mips/include/mcontext.h:1.23
--- src/sys/arch/mips/include/mcontext.h:1.22 Thu Feb 15 15:53:56 2018
+++ src/sys/arch/mips/include/mcontext.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.22 2018/02/15 15:53:56 kamil Exp $ */
+/* $NetBSD: mcontext.h,v 1.23 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
@@ -30,59 +30,59 @@
*/
#ifndef _MIPS_MCONTEXT_H_
-#define _MIPS_MCONTEXT_H_
+#define _MIPS_MCONTEXT_H_
/*
* General register state
*/
-#define _NGREG 37 /* R0-R31, MDLO, MDHI, CAUSE, PC, SR */
+#define _NGREG 37 /* R0-R31, MDLO, MDHI, CAUSE, PC, SR */
-#define _REG_R0 0
-#define _REG_AT 1
-#define _REG_V0 2
-#define _REG_V1 3
-#define _REG_A0 4
-#define _REG_A1 5
-#define _REG_A2 6
-#define _REG_A3 7
-#define _REG_T0 8
-#define _REG_T1 9
-#define _REG_T2 10
-#define _REG_T3 11
-#define _REG_T4 12
-#define _REG_T5 13
-#define _REG_T6 14
-#define _REG_T7 15
-#define _REG_S0 16
-#define _REG_S1 17
-#define _REG_S2 18
-#define _REG_S3 19
-#define _REG_S4 20
-#define _REG_S5 21
-#define _REG_S6 22
-#define _REG_S7 23
-#define _REG_T8 24
-#define _REG_T9 25
-#define _REG_K0 26
-#define _REG_K1 27
-#define _REG_GP 28
-#define _REG_SP 29
-#define _REG_S8 30
-#define _REG_RA 31
+#define _REG_R0 0
+#define _REG_AT 1
+#define _REG_V0 2
+#define _REG_V1 3
+#define _REG_A0 4
+#define _REG_A1 5
+#define _REG_A2 6
+#define _REG_A3 7
+#define _REG_T0 8
+#define _REG_T1 9
+#define _REG_T2 10
+#define _REG_T3 11
+#define _REG_T4 12
+#define _REG_T5 13
+#define _REG_T6 14
+#define _REG_T7 15
+#define _REG_S0 16
+#define _REG_S1 17
+#define _REG_S2 18
+#define _REG_S3 19
+#define _REG_S4 20
+#define _REG_S5 21
+#define _REG_S6 22
+#define _REG_S7 23
+#define _REG_T8 24
+#define _REG_T9 25
+#define _REG_K0 26
+#define _REG_K1 27
+#define _REG_GP 28
+#define _REG_SP 29
+#define _REG_S8 30
+#define _REG_RA 31
/* XXX: The following conflict with <mips/regnum.h> */
-#define _REG_MDLO 32
-#define _REG_MDHI 33
-#define _REG_CAUSE 34
-#define _REG_EPC 35
-#define _REG_SR 36
+#define _REG_MDLO 32
+#define _REG_MDHI 33
+#define _REG_CAUSE 34
+#define _REG_EPC 35
+#define _REG_SR 36
#ifndef __ASSEMBLER__
/* Make sure this is signed; we need pointers to be sign-extended. */
#if defined(__mips_n32)
typedef long long __greg_t;
-#else
+#else
typedef long __greg_t;
#endif /* __mips_n32 */
@@ -152,23 +152,23 @@ typedef struct {
#endif /* !__ASSEMBLER__ */
-#define _UC_MACHINE_PAD 14 /* Padding appended to ucontext_t */
+#define _UC_MACHINE_PAD 14 /* Padding appended to ucontext_t */
#define _UC_SETSTACK 0x00010000
#define _UC_CLRSTACK 0x00020000
#define _UC_TLSBASE 0x00040000
-#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
-#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_S8])
-#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_EPC])
-#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_V0])
+#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
+#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_S8])
+#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_EPC])
+#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_V0])
#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
-#define _UC_MACHINE32_SP(uc) _UC_MACHINE_SP(uc)
-#define _UC_MACHINE32_PC(uc) _UC_MACHINE_PC(uc)
-#define _UC_MACHINE32_INTRV(uc) _UC_MACHINE_INTRV(uc)
-#define _UC_MACHINE32_PAD 14 /* Padding appended to ucontext32_t */
+#define _UC_MACHINE32_SP(uc) _UC_MACHINE_SP(uc)
+#define _UC_MACHINE32_PC(uc) _UC_MACHINE_PC(uc)
+#define _UC_MACHINE32_INTRV(uc) _UC_MACHINE_INTRV(uc)
+#define _UC_MACHINE32_PAD 14 /* Padding appended to ucontext32_t */
#define _UC_MACHINE32_SET_PC(uc, pc) _UC_MACHINE_PC((uc), (pc))
@@ -210,14 +210,14 @@ __lwp_gettcb_fast(void)
// emulating rdhwr $3,$29 on a CN50xx
"addiu $2,$0,316; syscall; nop; move %[__tcb],$2"
#else
- ".set push"
+ ".set push"
";.set mips32r2"
";.p2align 4"
";ssnop"
";rdhwr $3,$29"
";ssnop"
";move %0,$3"
- ";.set pop"
+ ";.set pop"
#endif
: [__tcb]"=r"(__tcb)
:
Index: src/sys/arch/mips/include/mips1_pte.h
diff -u src/sys/arch/mips/include/mips1_pte.h:1.20 src/sys/arch/mips/include/mips1_pte.h:1.21
--- src/sys/arch/mips/include/mips1_pte.h:1.20 Fri Jun 26 22:56:36 2015
+++ src/sys/arch/mips/include/mips1_pte.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mips1_pte.h,v 1.20 2015/06/26 22:56:36 matt Exp $ */
+/* $NetBSD: mips1_pte.h,v 1.21 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#ifndef _MIPS_MIPS1_PTE_H_
-#define _MIPS_MIPS1_PTE_H_
+#define _MIPS_MIPS1_PTE_H_
/*
* R2000 hardware page table entry
*/
@@ -74,16 +74,16 @@ unsigned int pg_prot:2, /* SW: access c
#endif /* _LOCORE */
#define MIPS1_PG_PROT 0x00000003
-#define MIPS1_PG_RW 0x00000000
-#define MIPS1_PG_RO 0x00000001
-#define MIPS1_PG_WIRED 0x00000002
+#define MIPS1_PG_RW 0x00000000
+#define MIPS1_PG_RO 0x00000001
+#define MIPS1_PG_WIRED 0x00000002
#define MIPS1_PG_G 0x00000100
#define MIPS1_PG_V 0x00000200
#define MIPS1_PG_NV 0x00000000
#define MIPS1_PG_D 0x00000400
#define MIPS1_PG_N 0x00000800
#define MIPS1_PG_FRAME 0xfffff000
-#define MIPS1_PG_SHIFT 12
+#define MIPS1_PG_SHIFT 12
#define MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT)
#define MIPS1_PG_ROPAGE MIPS1_PG_V
@@ -97,6 +97,6 @@ unsigned int pg_prot:2, /* SW: access c
#define mips1_paddr_to_tlbpfn(x) (x)
#define MIPS1_PTE_TO_PADDR(pte) ((unsigned)(pte) & MIPS1_PG_FRAME)
-#define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO)
+#define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO)
#endif /* !_MIPS_MIPS1_PTE_H_ */
Index: src/sys/arch/mips/include/mips3_pte.h
diff -u src/sys/arch/mips/include/mips3_pte.h:1.29 src/sys/arch/mips/include/mips3_pte.h:1.30
--- src/sys/arch/mips/include/mips3_pte.h:1.29 Mon Jul 11 16:15:35 2016
+++ src/sys/arch/mips/include/mips3_pte.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mips3_pte.h,v 1.29 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: mips3_pte.h,v 1.30 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#ifndef _MIPS_MIPS3_PTE_H_
-#define _MIPS_MIPS3_PTE_H_
+#define _MIPS_MIPS3_PTE_H_
/*
* R4000 hardware page table entry
@@ -68,24 +68,24 @@ unsigned int pg_g:1, /* HW: ignore as
#endif
#endif /* _LOCORE */
-#define MIPS3_PG_WIRED 0x80000000 /* SW */
-#define MIPS3_PG_RO 0x40000000 /* SW */
+#define MIPS3_PG_WIRED 0x80000000 /* SW */
+#define MIPS3_PG_RO 0x40000000 /* SW */
#if PGSHIFT == 14
#define MIPS3_PG_SVPN (~0UL << 14) /* Software page no mask */
#define MIPS3_PG_HVPN (~0UL << 15) /* Hardware page no mask */
-#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
+#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
#elif PGSHIFT == 13
#ifdef MIPS3_4100
-#define 8KB page size is not supported on the MIPS3_4100
+#define 8KB page size is not supported on the MIPS3_4100
#endif
#define MIPS3_PG_SVPN (~0UL << 13) /* Software page no mask */
#define MIPS3_PG_HVPN (~0UL << 13) /* Hardware page no mask */
-#define MIPS3_PG_NEXT (1 << (12 - MIPS3_DEFAULT_PG_SHIFT))
+#define MIPS3_PG_NEXT (1 << (12 - MIPS3_DEFAULT_PG_SHIFT))
#elif PGSHIFT == 12
#define MIPS3_PG_SVPN (~0UL << 12) /* Software page no mask */
#define MIPS3_PG_HVPN (~0UL << 13) /* Hardware page no mask */
-#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
+#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
#endif
/* Odd even pte entry */
#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
@@ -139,28 +139,28 @@ unsigned int pg_g:1, /* HW: ignore as
(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca))
#define MIPS3_PG_FRAME 0x3fffffc0
-#define MIPS3_DEFAULT_PG_SHIFT 6
-#define MIPS3_4100_PG_SHIFT 4
+#define MIPS3_DEFAULT_PG_SHIFT 6
+#define MIPS3_4100_PG_SHIFT 4
/* NEC Vr4100 CPUs have different PFN layout to support 1kbytes/page */
#if defined(MIPS3_4100)
-#define MIPS3_PG_SHIFT mips_options.mips3_pg_shift
+#define MIPS3_PG_SHIFT mips_options.mips3_pg_shift
#else
-#define MIPS3_PG_SHIFT MIPS3_DEFAULT_PG_SHIFT
+#define MIPS3_PG_SHIFT MIPS3_DEFAULT_PG_SHIFT
#endif
/* pte accessor macros */
-#define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
-#define mips3_paddr_to_tlbpfn(x) \
+#define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
+#define mips3_paddr_to_tlbpfn(x) \
(((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
-#define mips3_tlbpfn_to_paddr(x) \
+#define mips3_tlbpfn_to_paddr(x) \
((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
-#define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN)
-#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
+#define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN)
+#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
-#define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte))
-#define MIPS3_PAGE_IS_RDONLY(pte,va) \
+#define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte))
+#define MIPS3_PAGE_IS_RDONLY(pte,va) \
(pmap_is_page_ro_p(pmap_kernel(), mips_trunc_page(va), (pte)))
Index: src/sys/arch/mips/include/mips_opcode.h
diff -u src/sys/arch/mips/include/mips_opcode.h:1.21 src/sys/arch/mips/include/mips_opcode.h:1.22
--- src/sys/arch/mips/include/mips_opcode.h:1.21 Sat Jun 27 03:30:01 2015
+++ src/sys/arch/mips/include/mips_opcode.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_opcode.h,v 1.21 2015/06/27 03:30:01 matt Exp $ */
+/* $NetBSD: mips_opcode.h,v 1.22 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -35,7 +35,7 @@
*/
#ifndef _MIPS_MIPS_OPCODE_H_
-#define _MIPS_MIPS_OPCODE_H_
+#define _MIPS_MIPS_OPCODE_H_
/*
* Define the instruction formats and opcode values for the
@@ -117,175 +117,175 @@ typedef union {
/*
* Values for the 'op' field.
*/
-#define OP_SPECIAL 000
-#define OP_REGIMM 001
-#define OP_J 002
-#define OP_JAL 003
-#define OP_BEQ 004
-#define OP_BNE 005
-#define OP_BLEZ 006
-#define OP_BGTZ 007
-
-#define OP_ADDI 010
-#define OP_ADDIU 011
-#define OP_SLTI 012
-#define OP_SLTIU 013
-#define OP_ANDI 014
-#define OP_ORI 015
-#define OP_XORI 016
-#define OP_LUI 017
-
-#define OP_COP0 020
-#define OP_COP1 021
-#define OP_COP2 022
-#define OP_COP3 023
-#define OP_BEQL 024 /* MIPS-II, for r4000 port */
-#define OP_BNEL 025 /* MIPS-II, for r4000 port */
-#define OP_BLEZL 026 /* MIPS-II, for r4000 port */
-#define OP_BGTZL 027 /* MIPS-II, for r4000 port */
-
-#define OP_DADDI 030 /* MIPS-II, for r4000 port */
-#define OP_DADDIU 031 /* MIPS-II, for r4000 port */
-#define OP_LDL 032 /* MIPS-II, for r4000 port */
-#define OP_LDR 033 /* MIPS-II, for r4000 port */
-
-#define OP_SPECIAL2 034 /* QED opcodes */
-#define OP_JALX 035
-#define OP_MDMX 036
-#define OP_SPECIAL3 037
-
-#define OP_LB 040
-#define OP_LH 041
-#define OP_LWL 042
-#define OP_LW 043
-#define OP_LBU 044
-#define OP_LHU 045
-#define OP_LWR 046
-#define OP_LHU 045
-#define OP_LWR 046
-#define OP_LWU 047 /* MIPS-II, for r4000 port */
-
-#define OP_SB 050
-#define OP_SH 051
-#define OP_SWL 052
-#define OP_SW 053
-#define OP_SDL 054 /* MIPS-II, for r4000 port */
-#define OP_SDR 055 /* MIPS-II, for r4000 port */
-#define OP_SWR 056
-#define OP_CACHE 057 /* MIPS-II, for r4000 port */
-
-#define OP_LL 060
-#define OP_LWC0 OP_LL /* backwards source compatibility */
-#define OP_LWC1 061
-#define OP_LWC2 062
-#define OP_PREF 063
-#define OP_LLD 064 /* MIPS-II, for r4000 port */
-#define OP_LDC1 065
-#define OP_LDC2 066
-#define OP_LD 067 /* MIPS-II, for r4000 port */
-#define OP_CVM_BBIT0 OP_LWC2
-#define OP_CVM_BBIT032 OP_LDC2
-
-#define OP_SC 070
-#define OP_SWC0 OP_SC /* backwards source compatibility */
-#define OP_SWC1 071
-#define OP_SWC2 072
-#define OP_RSVD073 073
-#define OP_SCD 074 /* MIPS-II, for r4000 port */
-#define OP_SDC1 075
-#define OP_SDC2 076
-#define OP_SD 077 /* MIPS-II, for r4000 port */
-#define OP_CVM_BBIT1 OP_SWC2
-#define OP_CVM_BBIT132 OP_SDC2
+#define OP_SPECIAL 000
+#define OP_REGIMM 001
+#define OP_J 002
+#define OP_JAL 003
+#define OP_BEQ 004
+#define OP_BNE 005
+#define OP_BLEZ 006
+#define OP_BGTZ 007
+
+#define OP_ADDI 010
+#define OP_ADDIU 011
+#define OP_SLTI 012
+#define OP_SLTIU 013
+#define OP_ANDI 014
+#define OP_ORI 015
+#define OP_XORI 016
+#define OP_LUI 017
+
+#define OP_COP0 020
+#define OP_COP1 021
+#define OP_COP2 022
+#define OP_COP3 023
+#define OP_BEQL 024 /* MIPS-II, for r4000 port */
+#define OP_BNEL 025 /* MIPS-II, for r4000 port */
+#define OP_BLEZL 026 /* MIPS-II, for r4000 port */
+#define OP_BGTZL 027 /* MIPS-II, for r4000 port */
+
+#define OP_DADDI 030 /* MIPS-II, for r4000 port */
+#define OP_DADDIU 031 /* MIPS-II, for r4000 port */
+#define OP_LDL 032 /* MIPS-II, for r4000 port */
+#define OP_LDR 033 /* MIPS-II, for r4000 port */
+
+#define OP_SPECIAL2 034 /* QED opcodes */
+#define OP_JALX 035
+#define OP_MDMX 036
+#define OP_SPECIAL3 037
+
+#define OP_LB 040
+#define OP_LH 041
+#define OP_LWL 042
+#define OP_LW 043
+#define OP_LBU 044
+#define OP_LHU 045
+#define OP_LWR 046
+#define OP_LHU 045
+#define OP_LWR 046
+#define OP_LWU 047 /* MIPS-II, for r4000 port */
+
+#define OP_SB 050
+#define OP_SH 051
+#define OP_SWL 052
+#define OP_SW 053
+#define OP_SDL 054 /* MIPS-II, for r4000 port */
+#define OP_SDR 055 /* MIPS-II, for r4000 port */
+#define OP_SWR 056
+#define OP_CACHE 057 /* MIPS-II, for r4000 port */
+
+#define OP_LL 060
+#define OP_LWC0 OP_LL /* backwards source compatibility */
+#define OP_LWC1 061
+#define OP_LWC2 062
+#define OP_PREF 063
+#define OP_LLD 064 /* MIPS-II, for r4000 port */
+#define OP_LDC1 065
+#define OP_LDC2 066
+#define OP_LD 067 /* MIPS-II, for r4000 port */
+#define OP_CVM_BBIT0 OP_LWC2
+#define OP_CVM_BBIT032 OP_LDC2
+
+#define OP_SC 070
+#define OP_SWC0 OP_SC /* backwards source compatibility */
+#define OP_SWC1 071
+#define OP_SWC2 072
+#define OP_RSVD073 073
+#define OP_SCD 074 /* MIPS-II, for r4000 port */
+#define OP_SDC1 075
+#define OP_SDC2 076
+#define OP_SD 077 /* MIPS-II, for r4000 port */
+#define OP_CVM_BBIT1 OP_SWC2
+#define OP_CVM_BBIT132 OP_SDC2
/*
* Values for the 'func' field when 'op' == OP_SPECIAL.
*/
-#define OP_SLL 000
-#define OP_SRL 002
-#define OP_SRA 003
-#define OP_SLLV 004
-#define OP_SRLV 006
-#define OP_SRAV 007
-
-#define OP_JR 010
-#define OP_JALR 011
-#define OP_SYSCALL 014
-#define OP_BREAK 015
-#define OP_SYNC 017 /* MIPS-II, for r4000 port */
-
-#define SYNC_CVM_IODBDMA 0x02
-#define SYNC_WMB 0x04
-#define SYNC_CVM_W SYNC_WMB
-#define SYNC_CVM_WS 0x05
-#define SYNC_CVM_S 0x06
-#define SYNC_MB 0x10
-#define SYNC_ACQUIRE 0x11
-#define SYNC_RELEASE 0x12
-#define SYNC_RMB 0x13
-
-#define OP_MFHI 020
-#define OP_MTHI 021
-#define OP_MFLO 022
-#define OP_MTLO 023
-#define OP_DSLLV 024 /* MIPS-II, for r4000 port */
-#define OP_DSRLV 026 /* MIPS-II, for r4000 port */
-#define OP_DSRAV 027 /* MIPS-II, for r4000 port */
-
-#define OP_MULT 030
-#define OP_MULTU 031
-#define OP_DIV 032
-#define OP_DIVU 033
-#define OP_DMULT 034 /* MIPS-II, for r4000 port */
-#define OP_DMULTU 035 /* MIPS-II, for r4000 port */
-#define OP_DDIV 036 /* MIPS-II, for r4000 port */
-#define OP_DDIVU 037 /* MIPS-II, for r4000 port */
-
-#define OP_ADD 040
-#define OP_ADDU 041
-#define OP_SUB 042
-#define OP_SUBU 043
-#define OP_AND 044
-#define OP_OR 045
-#define OP_XOR 046
-#define OP_NOR 047
-
-#define OP_SLT 052
-#define OP_SLTU 053
-#define OP_DADD 054 /* MIPS-II, for r4000 port */
-#define OP_DADDU 055 /* MIPS-II, for r4000 port */
-#define OP_DSUB 056 /* MIPS-II, for r4000 port */
-#define OP_DSUBU 057 /* MIPS-II, for r4000 port */
-
-#define OP_TGE 060 /* MIPS-II, for r4000 port */
-#define OP_TGEU 061 /* MIPS-II, for r4000 port */
-#define OP_TLT 062 /* MIPS-II, for r4000 port */
-#define OP_TLTU 063 /* MIPS-II, for r4000 port */
-#define OP_TEQ 064 /* MIPS-II, for r4000 port */
-#define OP_TNE 066 /* MIPS-II, for r4000 port */
-
-#define OP_DSLL 070 /* MIPS-II, for r4000 port */
-#define OP_DSRL 072 /* MIPS-II, for r4000 port */
-#define OP_DSRA 073 /* MIPS-II, for r4000 port */
-#define OP_DSLL32 074 /* MIPS-II, for r4000 port */
-#define OP_DSRL32 076 /* MIPS-II, for r4000 port */
-#define OP_DSRA32 077 /* MIPS-II, for r4000 port */
+#define OP_SLL 000
+#define OP_SRL 002
+#define OP_SRA 003
+#define OP_SLLV 004
+#define OP_SRLV 006
+#define OP_SRAV 007
+
+#define OP_JR 010
+#define OP_JALR 011
+#define OP_SYSCALL 014
+#define OP_BREAK 015
+#define OP_SYNC 017 /* MIPS-II, for r4000 port */
+
+#define SYNC_CVM_IODBDMA 0x02
+#define SYNC_WMB 0x04
+#define SYNC_CVM_W SYNC_WMB
+#define SYNC_CVM_WS 0x05
+#define SYNC_CVM_S 0x06
+#define SYNC_MB 0x10
+#define SYNC_ACQUIRE 0x11
+#define SYNC_RELEASE 0x12
+#define SYNC_RMB 0x13
+
+#define OP_MFHI 020
+#define OP_MTHI 021
+#define OP_MFLO 022
+#define OP_MTLO 023
+#define OP_DSLLV 024 /* MIPS-II, for r4000 port */
+#define OP_DSRLV 026 /* MIPS-II, for r4000 port */
+#define OP_DSRAV 027 /* MIPS-II, for r4000 port */
+
+#define OP_MULT 030
+#define OP_MULTU 031
+#define OP_DIV 032
+#define OP_DIVU 033
+#define OP_DMULT 034 /* MIPS-II, for r4000 port */
+#define OP_DMULTU 035 /* MIPS-II, for r4000 port */
+#define OP_DDIV 036 /* MIPS-II, for r4000 port */
+#define OP_DDIVU 037 /* MIPS-II, for r4000 port */
+
+#define OP_ADD 040
+#define OP_ADDU 041
+#define OP_SUB 042
+#define OP_SUBU 043
+#define OP_AND 044
+#define OP_OR 045
+#define OP_XOR 046
+#define OP_NOR 047
+
+#define OP_SLT 052
+#define OP_SLTU 053
+#define OP_DADD 054 /* MIPS-II, for r4000 port */
+#define OP_DADDU 055 /* MIPS-II, for r4000 port */
+#define OP_DSUB 056 /* MIPS-II, for r4000 port */
+#define OP_DSUBU 057 /* MIPS-II, for r4000 port */
+
+#define OP_TGE 060 /* MIPS-II, for r4000 port */
+#define OP_TGEU 061 /* MIPS-II, for r4000 port */
+#define OP_TLT 062 /* MIPS-II, for r4000 port */
+#define OP_TLTU 063 /* MIPS-II, for r4000 port */
+#define OP_TEQ 064 /* MIPS-II, for r4000 port */
+#define OP_TNE 066 /* MIPS-II, for r4000 port */
+
+#define OP_DSLL 070 /* MIPS-II, for r4000 port */
+#define OP_DSRL 072 /* MIPS-II, for r4000 port */
+#define OP_DSRA 073 /* MIPS-II, for r4000 port */
+#define OP_DSLL32 074 /* MIPS-II, for r4000 port */
+#define OP_DSRL32 076 /* MIPS-II, for r4000 port */
+#define OP_DSRA32 077 /* MIPS-II, for r4000 port */
/*
* Values for the 'func' field when 'op' == OP_SPECIAL2.
*/
-#define OP_MADD 000 /* QED */
-#define OP_MADDU 001 /* QED */
-#define OP_MUL 002 /* QED */
+#define OP_MADD 000 /* QED */
+#define OP_MADDU 001 /* QED */
+#define OP_MUL 002 /* QED */
#define OP_CVM_DMUL 003 /* OCTEON */
-#define OP_MSUB 004 /* MIPS32/64 */
-#define OP_MSUBU 005 /* MIPS32/64 */
+#define OP_MSUB 004 /* MIPS32/64 */
+#define OP_MSUBU 005 /* MIPS32/64 */
#define OP_CVM_SAA 030 /* OCTEON */
#define OP_CVM_SAAD 031 /* OCTEON */
-#define OP_CLZ 040 /* MIPS32/64 */
-#define OP_CLO 041 /* MIPS32/64 */
-#define OP_DCLZ 044 /* MIPS32/64 */
-#define OP_DCLO 045 /* MIPS32/64 */
+#define OP_CLZ 040 /* MIPS32/64 */
+#define OP_CLO 041 /* MIPS32/64 */
+#define OP_DCLZ 044 /* MIPS32/64 */
+#define OP_DCLO 045 /* MIPS32/64 */
#define OP_CVM_BADDU 050 /* OCTEON */
#define OP_CVM_SEQ 052 /* OCTEON */
#define OP_CVM_SNE 053 /* OCTEON */
@@ -302,39 +302,39 @@ typedef union {
/*
* Values for the 'func' field when 'op' == OP_SPECIAL3.
*/
-#define OP_EXT 000 /* MIPS32/64 r2 */
-#define OP_DEXTM 001 /* MIPS32/64 r2 */
-#define OP_DEXTU 002 /* MIPS32/64 r2 */
-#define OP_DEXT 003 /* MIPS32/64 r2 */
-#define OP_INS 004 /* MIPS32/64 r2 */
-#define OP_DINSM 005 /* MIPS32/64 r2 */
-#define OP_DINSU 006 /* MIPS32/64 r2 */
-#define OP_DINS 007 /* MIPS32/64 r2 */
+#define OP_EXT 000 /* MIPS32/64 r2 */
+#define OP_DEXTM 001 /* MIPS32/64 r2 */
+#define OP_DEXTU 002 /* MIPS32/64 r2 */
+#define OP_DEXT 003 /* MIPS32/64 r2 */
+#define OP_INS 004 /* MIPS32/64 r2 */
+#define OP_DINSM 005 /* MIPS32/64 r2 */
+#define OP_DINSU 006 /* MIPS32/64 r2 */
+#define OP_DINS 007 /* MIPS32/64 r2 */
#define OP_LX 012 /* DSP */
-#define OP_LWLE 031 /* EVA */
-#define OP_LWRE 032 /* EVA */
-#define OP_CACHEE 033 /* EVA */
-#define OP_SBE 034 /* EVA */
-#define OP_SHE 035 /* EVA */
-#define OP_SCE 035 /* EVA */
-#define OP_SWE 035 /* EVA */
-#define OP_BSHFL 040 /* MIPS32/64 r2 */
-#define OP_SWLE 041 /* EVA */
-#define OP_SWRE 042 /* EVA */
-#define OP_PREFE 043 /* EVA */
-#define OP_DBSHFL 044 /* MIPS32/64 r2 */
-#define OP_LBUE 050 /* EVA */
-#define OP_LHUE 051 /* EVA */
-#define OP_LBE 054 /* EVA */
-#define OP_LHE 055 /* EVA */
-#define OP_LLE 056 /* EVA */
-#define OP_LWE 057 /* EVA */
-#define OP_RDHWR 073 /* MIPS32/64 r2 */
-
-#define OP_BSHFL_SBH 002 /* swap bytes within halfwords */
-#define OP_BSHFL_SHD 005 /* swap halfworks within double */
-#define OP_BSHFL_SEB 020 /* sign extend byte */
-#define OP_BSHFL_SEH 030 /* sign extend halfword */
+#define OP_LWLE 031 /* EVA */
+#define OP_LWRE 032 /* EVA */
+#define OP_CACHEE 033 /* EVA */
+#define OP_SBE 034 /* EVA */
+#define OP_SHE 035 /* EVA */
+#define OP_SCE 035 /* EVA */
+#define OP_SWE 035 /* EVA */
+#define OP_BSHFL 040 /* MIPS32/64 r2 */
+#define OP_SWLE 041 /* EVA */
+#define OP_SWRE 042 /* EVA */
+#define OP_PREFE 043 /* EVA */
+#define OP_DBSHFL 044 /* MIPS32/64 r2 */
+#define OP_LBUE 050 /* EVA */
+#define OP_LHUE 051 /* EVA */
+#define OP_LBE 054 /* EVA */
+#define OP_LHE 055 /* EVA */
+#define OP_LLE 056 /* EVA */
+#define OP_LWE 057 /* EVA */
+#define OP_RDHWR 073 /* MIPS32/64 r2 */
+
+#define OP_BSHFL_SBH 002 /* swap bytes within halfwords */
+#define OP_BSHFL_SHD 005 /* swap halfworks within double */
+#define OP_BSHFL_SEB 020 /* sign extend byte */
+#define OP_BSHFL_SEH 030 /* sign extend halfword */
#define OP_LX_LWX 0 /* lwx */
#define OP_LX_LHX 4 /* lhx */
@@ -344,47 +344,47 @@ typedef union {
/*
* Values for the 'func' field when 'op' == OP_REGIMM.
*/
-#define OP_BLTZ 000
-#define OP_BGEZ 001
-#define OP_BLTZL 002 /* MIPS-II, for r4000 port */
-#define OP_BGEZL 003 /* MIPS-II, for r4000 port */
-
-#define OP_TGEI 010 /* MIPS-II, for r4000 port */
-#define OP_TGEIU 011 /* MIPS-II, for r4000 port */
-#define OP_TLTI 012 /* MIPS-II, for r4000 port */
-#define OP_TLTIU 013 /* MIPS-II, for r4000 port */
-#define OP_TEQI 014 /* MIPS-II, for r4000 port */
-#define OP_TNEI 016 /* MIPS-II, for r4000 port */
-
-#define OP_BLTZAL 020 /* MIPS-II, for r4000 port */
-#define OP_BGEZAL 021
-#define OP_BLTZALL 022
-#define OP_BGEZALL 023
+#define OP_BLTZ 000
+#define OP_BGEZ 001
+#define OP_BLTZL 002 /* MIPS-II, for r4000 port */
+#define OP_BGEZL 003 /* MIPS-II, for r4000 port */
+
+#define OP_TGEI 010 /* MIPS-II, for r4000 port */
+#define OP_TGEIU 011 /* MIPS-II, for r4000 port */
+#define OP_TLTI 012 /* MIPS-II, for r4000 port */
+#define OP_TLTIU 013 /* MIPS-II, for r4000 port */
+#define OP_TEQI 014 /* MIPS-II, for r4000 port */
+#define OP_TNEI 016 /* MIPS-II, for r4000 port */
+
+#define OP_BLTZAL 020 /* MIPS-II, for r4000 port */
+#define OP_BGEZAL 021
+#define OP_BLTZALL 022
+#define OP_BGEZALL 023
/*
* Values for the 'rs' field when 'op' == OP_COPz.
*/
-#define OP_MF 000
-#define OP_DMF 001 /* MIPS-II, for r4000 port */
-#define OP_CF 002
-#define OP_MFH 003
-#define OP_MT 004
-#define OP_DMT 005 /* MIPS-II, for r4000 port */
-#define OP_CT 006
-#define OP_MTH 007
-#define OP_BCx 010
-#define OP_MFM 013 /* MIPS32/64 r2 */
-#define OP_BCy 014
+#define OP_MF 000
+#define OP_DMF 001 /* MIPS-II, for r4000 port */
+#define OP_CF 002
+#define OP_MFH 003
+#define OP_MT 004
+#define OP_DMT 005 /* MIPS-II, for r4000 port */
+#define OP_CT 006
+#define OP_MTH 007
+#define OP_BCx 010
+#define OP_MFM 013 /* MIPS32/64 r2 */
+#define OP_BCy 014
/*
* Values for the 'rt' field when 'op' == OP_COPz.
*/
-#define COPz_BC_TF_MASK 0x01
-#define COPz_BC_TRUE 0x01
-#define COPz_BC_FALSE 0x00
-#define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */
-#define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */
-#define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */
+#define COPz_BC_TF_MASK 0x01
+#define COPz_BC_TRUE 0x01
+#define COPz_BC_FALSE 0x00
+#define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */
+#define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */
+#define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */
#define INSN_LUI_P(insn) (((insn) >> 26) == OP_LUI)
#define INSN_LW_P(insn) (((insn) >> 26) == OP_LW)
@@ -392,7 +392,7 @@ typedef union {
#define INSN_LD_P(insn) (((insn) >> 26) == OP_LD)
#define INSN_SD_P(insn) (((insn) >> 26) == OP_SD)
-#define INSN_LOAD_P(insn) (INSN_LD_P(insn) || INSN_LW_P(insn))
-#define INSN_STORE_P(insn) (INSN_SD_P(insn) || INSN_SW_P(insn))
+#define INSN_LOAD_P(insn) (INSN_LD_P(insn) || INSN_LW_P(insn))
+#define INSN_STORE_P(insn) (INSN_SD_P(insn) || INSN_SW_P(insn))
#endif /* _MIPS_MIPS_OPCODE_H_ */
Index: src/sys/arch/mips/include/profile.h
diff -u src/sys/arch/mips/include/profile.h:1.21 src/sys/arch/mips/include/profile.h:1.22
--- src/sys/arch/mips/include/profile.h:1.21 Sun Feb 20 07:45:47 2011
+++ src/sys/arch/mips/include/profile.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: profile.h,v 1.21 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: profile.h,v 1.22 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -35,7 +35,7 @@
*/
#ifndef _MIPS_PROFILE_H_
-#define _MIPS_PROFILE_H_
+#define _MIPS_PROFILE_H_
#ifdef _KERNEL
/*
Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.44 src/sys/arch/mips/include/mips_param.h:1.45
--- src/sys/arch/mips/include/mips_param.h:1.44 Sun Jul 26 07:13:51 2020
+++ src/sys/arch/mips/include/mips_param.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_param.h,v 1.44 2020/07/26 07:13:51 simonb Exp $ */
+/* $NetBSD: mips_param.h,v 1.45 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -58,11 +58,11 @@
*/
#ifndef _KERNEL
#undef MACHINE
-#define MACHINE "mips"
+#define MACHINE "mips"
#endif
-#define ALIGNBYTES32 (sizeof(double) - 1)
-#define ALIGN32(p) (((uintptr_t)(p) + ALIGNBYTES32) &~ALIGNBYTES32)
+#define ALIGNBYTES32 (sizeof(double) - 1)
+#define ALIGN32(p) (((uintptr_t)(p) + ALIGNBYTES32) &~ALIGNBYTES32)
/*
* On mips, UPAGES is fixed by sys/arch/mips/mips/locore code
@@ -77,15 +77,15 @@
#endif
#ifndef MSGBUFSIZE
-#define MSGBUFSIZE NBPG /* default message buffer size */
+#define MSGBUFSIZE NBPG /* default message buffer size */
#endif
/*
* Most MIPS have a cache line size of 32 bytes, but Cavium chips
* have a line size 128 bytes and we need to cover the larger size.
*/
-#define COHERENCY_UNIT 128
-#define CACHE_LINE_SIZE 128
+#define COHERENCY_UNIT 128
+#define CACHE_LINE_SIZE 128
#ifdef ENABLE_MIPS_16KB_PAGE
#define PGSHIFT 14 /* LOG2(NBPG) */
@@ -135,10 +135,10 @@
/*
* Mach derived conversion macros
*/
-#define mips_round_page(x) ((((uintptr_t)(x)) + NBPG - 1) & ~(NBPG-1))
-#define mips_trunc_page(x) ((uintptr_t)(x) & ~(NBPG-1))
-#define mips_btop(x) ((paddr_t)(x) >> PGSHIFT)
-#define mips_ptob(x) ((paddr_t)(x) << PGSHIFT)
+#define mips_round_page(x) ((((uintptr_t)(x)) + NBPG - 1) & ~(NBPG-1))
+#define mips_trunc_page(x) ((uintptr_t)(x) & ~(NBPG-1))
+#define mips_btop(x) ((paddr_t)(x) >> PGSHIFT)
+#define mips_ptob(x) ((paddr_t)(x) << PGSHIFT)
#ifdef __MIPSEL__
#define MID_MACHINE MID_PMAX /* MID_PMAX (little-endian) */
Index: src/sys/arch/mips/include/pmap.h
diff -u src/sys/arch/mips/include/pmap.h:1.71 src/sys/arch/mips/include/pmap.h:1.72
--- src/sys/arch/mips/include/pmap.h:1.71 Mon Apr 1 06:12:51 2019
+++ src/sys/arch/mips/include/pmap.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.71 2019/04/01 06:12:51 msaitoh Exp $ */
+/* $NetBSD: pmap.h,v 1.72 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -85,37 +85,37 @@
#include <sys/kernhist.h>
#ifndef __BSD_PTENTRY_T__
-#define __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
typedef uint32_t pt_entry_t;
-#define PRIxPTE PRIx32
+#define PRIxPTE PRIx32
#endif /* __BSD_PTENTRY_T__ */
-#define KERNEL_PID 0
+#define KERNEL_PID 0
#if defined(__PMAP_PRIVATE)
#include <mips/locore.h>
#include <mips/cache.h>
-#define PMAP_VIRTUAL_CACHE_ALIASES
-#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)NULL)
+#define PMAP_VIRTUAL_CACHE_ALIASES
+#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)NULL)
#define PMAP_TLB_NEED_SHOOTDOWN
-#define PMAP_TLB_FLUSH_ASID_ON_RESET false
+#define PMAP_TLB_FLUSH_ASID_ON_RESET false
#if UPAGES > 1
-#define PMAP_TLB_WIRED_UPAGES MIPS3_TLB_WIRED_UPAGES
+#define PMAP_TLB_WIRED_UPAGES MIPS3_TLB_WIRED_UPAGES
#endif
-#define pmap_md_tlb_asid_max() (MIPS_TLB_NUM_PIDS - 1)
+#define pmap_md_tlb_asid_max() (MIPS_TLB_NUM_PIDS - 1)
#ifdef MULTIPROCESSOR
-#define PMAP_NO_PV_UNCACHED
+#define PMAP_NO_PV_UNCACHED
#endif
/*
* We need the pmap_segtab's to be aligned on MIPS*R2 so we can use the
* EXT/INS instructions on their addresses.
- */
+ */
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
-#define PMAP_SEGTAB_ALIGN __aligned(sizeof(void *)*NSEGPG) __section(".data1")
-#endif
+#define PMAP_SEGTAB_ALIGN __aligned(sizeof(void *)*NSEGPG) __section(".data1")
+#endif
#include <uvm/uvm_physseg.h>
@@ -155,9 +155,9 @@ struct tlbmask {
};
#ifdef _LP64
-#define PMAP_SEGTABSIZE NSEGPG
+#define PMAP_SEGTABSIZE NSEGPG
#else
-#define PMAP_SEGTABSIZE (1 << (31 - SEGSHIFT))
+#define PMAP_SEGTABSIZE (1 << (31 - SEGSHIFT))
#endif
#include <uvm/pmap/vmpagemd.h>
@@ -172,8 +172,8 @@ struct tlbmask {
#define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */
#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
-#define PGC_NOCACHE 0x4000000000000000ULL
-#define PGC_PREFETCH 0x2000000000000000ULL
+#define PGC_NOCACHE 0x4000000000000000ULL
+#define PGC_PREFETCH 0x2000000000000000ULL
#endif
#if defined(__PMAP_PRIVATE)
@@ -202,7 +202,7 @@ struct tlbmask {
* dynamically allocated at boot time.
*/
-#define pmap_phys_address(x) mips_ptob(x)
+#define pmap_phys_address(x) mips_ptob(x)
/*
* Bootstrap the system enough to run with virtual memory.
@@ -217,7 +217,7 @@ void pmap_procwr(struct proc *, vaddr_t,
* the virtually-indexed cache on mips3 CPUs.
*/
#ifdef MIPS3_PLUS
-#define PMAP_PREFER(pa, va, sz, td) pmap_prefer((pa), (va), (sz), (td))
+#define PMAP_PREFER(pa, va, sz, td) pmap_prefer((pa), (va), (sz), (td))
void pmap_prefer(vaddr_t, vaddr_t *, vsize_t, int);
#endif /* MIPS3_PLUS */
Index: src/sys/arch/mips/include/proc.h
diff -u src/sys/arch/mips/include/proc.h:1.28 src/sys/arch/mips/include/proc.h:1.29
--- src/sys/arch/mips/include/proc.h:1.28 Tue Jun 30 04:20:19 2015
+++ src/sys/arch/mips/include/proc.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.28 2015/06/30 04:20:19 matt Exp $ */
+/* $NetBSD: proc.h,v 1.29 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -35,7 +35,7 @@
*/
#ifndef _MIPS_PROC_H_
-#define _MIPS_PROC_H_
+#define _MIPS_PROC_H_
#include <sys/param.h>
#include <mips/vmparam.h>
Index: src/sys/arch/mips/include/pte.h
diff -u src/sys/arch/mips/include/pte.h:1.25 src/sys/arch/mips/include/pte.h:1.26
--- src/sys/arch/mips/include/pte.h:1.25 Sat Jun 24 07:00:37 2017
+++ src/sys/arch/mips/include/pte.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.25 2017/06/24 07:00:37 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.26 2020/07/26 08:08:41 simonb Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -44,7 +44,7 @@
*/
#ifndef __MIPS_PTE_H__
-#define __MIPS_PTE_H__
+#define __MIPS_PTE_H__
#include <mips/mips1_pte.h>
#include <mips/mips3_pte.h>
@@ -53,9 +53,9 @@
#ifndef _LOCORE
#ifndef __BSD_PTENTRY_T__
-#define __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
typedef uint32_t pt_entry_t;
-#define PRIxPTE PRIx32
+#define PRIxPTE PRIx32
#endif
/*
@@ -256,7 +256,7 @@ mips_paddr_to_tlbpfn(paddr_t pa)
#endif /* ! _LOCORE */
#if defined(_KERNEL) && !defined(_LOCORE)
-#define MIPS_MMU(X) (MIPS_HAS_R4K_MMU ? MIPS3_##X : MIPS1_##X)
+#define MIPS_MMU(X) (MIPS_HAS_R4K_MMU ? MIPS3_##X : MIPS1_##X)
static inline bool
pte_valid_p(pt_entry_t pte)
{
Index: src/sys/arch/mips/include/reg.h
diff -u src/sys/arch/mips/include/reg.h:1.18 src/sys/arch/mips/include/reg.h:1.19
--- src/sys/arch/mips/include/reg.h:1.18 Fri Dec 29 09:27:01 2017
+++ src/sys/arch/mips/include/reg.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.18 2017/12/29 09:27:01 maya Exp $ */
+/* $NetBSD: reg.h,v 1.19 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -39,7 +39,7 @@
*/
#ifndef _MIPS_REG_H_
-#define _MIPS_REG_H_
+#define _MIPS_REG_H_
struct reg {
Index: src/sys/arch/mips/include/regdef.h
diff -u src/sys/arch/mips/include/regdef.h:1.13 src/sys/arch/mips/include/regdef.h:1.14
--- src/sys/arch/mips/include/regdef.h:1.13 Sun Jun 7 06:07:49 2015
+++ src/sys/arch/mips/include/regdef.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: regdef.h,v 1.13 2015/06/07 06:07:49 matt Exp $ */
+/* $NetBSD: regdef.h,v 1.14 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -36,18 +36,18 @@
*/
#ifndef _MIPS_REGDEF_H
-#define _MIPS_REGDEF_H
+#define _MIPS_REGDEF_H
#include <machine/cdefs.h> /* for API selection */
-#define zero $0 /* always zero */
-#define AT $at /* assembler temporary */
-#define v0 $2 /* return value */
-#define v1 $3
-#define a0 $4 /* argument registers */
-#define a1 $5
-#define a2 $6
-#define a3 $7
+#define zero $0 /* always zero */
+#define AT $at /* assembler temporary */
+#define v0 $2 /* return value */
+#define v1 $3
+#define a0 $4 /* argument registers */
+#define a1 $5
+#define a2 $6
+#define a3 $7
#if defined(__mips_n32) || defined(__mips_n64)
#define a4 $8
#define a5 $9
@@ -58,31 +58,31 @@
#define t2 $14
#define t3 $15
#else
-#define t0 $8 /* temp registers (not saved across subroutine calls) */
-#define t1 $9
-#define t2 $10
-#define t3 $11
-#define t4 $12
-#define t5 $13
-#define t6 $14
-#define t7 $15
+#define t0 $8 /* temp registers (not saved across subroutine calls) */
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
#endif /* __mips_n32 || __mips_n64 */
-#define s0 $16 /* saved across subroutine calls (callee saved) */
-#define s1 $17
-#define s2 $18
-#define s3 $19
-#define s4 $20
-#define s5 $21
-#define s6 $22
-#define s7 $23
-#define t8 $24 /* two more temporary registers */
-#define t9 $25
-#define k0 $26 /* kernel temporary */
-#define k1 $27
-#define gp $28 /* global pointer */
-#define sp $29 /* stack pointer */
-#define s8 $30 /* one more callee saved */
-#define ra $31 /* return address */
+#define s0 $16 /* saved across subroutine calls (callee saved) */
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24 /* two more temporary registers */
+#define t9 $25
+#define k0 $26 /* kernel temporary */
+#define k1 $27
+#define gp $28 /* global pointer */
+#define sp $29 /* stack pointer */
+#define s8 $30 /* one more callee saved */
+#define ra $31 /* return address */
/*
* These are temp registers whose names can be used in either the old
Index: src/sys/arch/mips/include/regnum.h
diff -u src/sys/arch/mips/include/regnum.h:1.11 src/sys/arch/mips/include/regnum.h:1.12
--- src/sys/arch/mips/include/regnum.h:1.11 Tue Aug 16 06:58:15 2011
+++ src/sys/arch/mips/include/regnum.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: regnum.h,v 1.11 2011/08/16 06:58:15 matt Exp $ */
+/* $NetBSD: regnum.h,v 1.12 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -43,49 +43,49 @@
* registers relative to ZERO.
* Usage is p->p_regs[XX].
*/
-#define _R_ZERO 0 /* hardware zero */
-#define _R_AST 1 /* caller-saved */
-#define _R_V0 2 /* caller-saved */
-#define _R_V1 3 /* caller-saved */
-#define _R_A0 4 /* caller-saved */
-#define _R_A1 5 /* caller-saved */
-#define _R_A2 6 /* caller-saved */
-#define _R_A3 7 /* caller-saved */
+#define _R_ZERO 0 /* hardware zero */
+#define _R_AST 1 /* caller-saved */
+#define _R_V0 2 /* caller-saved */
+#define _R_V1 3 /* caller-saved */
+#define _R_A0 4 /* caller-saved */
+#define _R_A1 5 /* caller-saved */
+#define _R_A2 6 /* caller-saved */
+#define _R_A3 7 /* caller-saved */
#if defined(__mips_n32) || defined(__mips_n64)
-#define _R_A4 8 /* caller-saved */
-#define _R_A5 9 /* caller-saved */
-#define _R_A6 10 /* caller-saved */
-#define _R_A7 11 /* caller-saved */
-#define _R_T0 12 /* caller-saved */
-#define _R_T1 13 /* caller-saved */
-#define _R_T2 14 /* caller-saved */
-#define _R_T3 15 /* caller-saved */
+#define _R_A4 8 /* caller-saved */
+#define _R_A5 9 /* caller-saved */
+#define _R_A6 10 /* caller-saved */
+#define _R_A7 11 /* caller-saved */
+#define _R_T0 12 /* caller-saved */
+#define _R_T1 13 /* caller-saved */
+#define _R_T2 14 /* caller-saved */
+#define _R_T3 15 /* caller-saved */
#else
-#define _R_T0 8 /* caller-saved */
-#define _R_T1 9 /* caller-saved */
-#define _R_T2 10 /* caller-saved */
-#define _R_T3 11 /* caller-saved */
-#define _R_T4 12 /* caller-saved */
-#define _R_T5 13 /* caller-saved */
-#define _R_T6 14 /* caller-saved */
-#define _R_T7 15 /* caller-saved */
+#define _R_T0 8 /* caller-saved */
+#define _R_T1 9 /* caller-saved */
+#define _R_T2 10 /* caller-saved */
+#define _R_T3 11 /* caller-saved */
+#define _R_T4 12 /* caller-saved */
+#define _R_T5 13 /* caller-saved */
+#define _R_T6 14 /* caller-saved */
+#define _R_T7 15 /* caller-saved */
#endif /* __mips_n32 || __mips_n64 */
-#define _R_S0 16 /* CALLEE-saved */
-#define _R_S1 17 /* CALLEE-saved */
-#define _R_S2 18 /* CALLEE-saved */
-#define _R_S3 19 /* CALLEE-saved */
-#define _R_S4 20 /* CALLEE-saved */
-#define _R_S5 21 /* CALLEE-saved */
-#define _R_S6 22 /* CALLEE-saved */
-#define _R_S7 23 /* CALLEE-saved */
-#define _R_T8 24 /* caller-saved */
-#define _R_T9 25 /* caller-saved */
-#define _R_K0 26 /* kernel reserved */
-#define _R_K1 27 /* kernel reserved */
-#define _R_GP 28 /* CALLEE-saved */
-#define _R_SP 29 /* CALLEE-saved */
-#define _R_S8 30 /* CALLEE-saved */
-#define _R_RA 31 /* caller-saved */
+#define _R_S0 16 /* CALLEE-saved */
+#define _R_S1 17 /* CALLEE-saved */
+#define _R_S2 18 /* CALLEE-saved */
+#define _R_S3 19 /* CALLEE-saved */
+#define _R_S4 20 /* CALLEE-saved */
+#define _R_S5 21 /* CALLEE-saved */
+#define _R_S6 22 /* CALLEE-saved */
+#define _R_S7 23 /* CALLEE-saved */
+#define _R_T8 24 /* caller-saved */
+#define _R_T9 25 /* caller-saved */
+#define _R_K0 26 /* kernel reserved */
+#define _R_K1 27 /* kernel reserved */
+#define _R_GP 28 /* CALLEE-saved */
+#define _R_SP 29 /* CALLEE-saved */
+#define _R_S8 30 /* CALLEE-saved */
+#define _R_RA 31 /* caller-saved */
#define _R_SR 32
#define _R_PS _R_SR /* alias for SR */
@@ -102,52 +102,52 @@
#define _R_TA3 15
#endif /* __mips_n32 || __mips_n64 */
-#define _R_MULLO 33
-#define _R_MULHI 34
-#define _R_BADVADDR 35
-#define _R_CAUSE 36
+#define _R_MULLO 33
+#define _R_MULHI 34
+#define _R_BADVADDR 35
+#define _R_CAUSE 36
#define _R_PC 37
-#define _FPBASE (_R_PC + 1)
-#define _R_F0 (_FPBASE+0)
-#define _R_F1 (_FPBASE+1)
-#define _R_F2 (_FPBASE+2)
-#define _R_F3 (_FPBASE+3)
-#define _R_F4 (_FPBASE+4)
-#define _R_F5 (_FPBASE+5)
-#define _R_F6 (_FPBASE+6)
-#define _R_F7 (_FPBASE+7)
-#define _R_F8 (_FPBASE+8)
-#define _R_F9 (_FPBASE+9)
-#define _R_F10 (_FPBASE+10)
-#define _R_F11 (_FPBASE+11)
-#define _R_F12 (_FPBASE+12)
-#define _R_F13 (_FPBASE+13)
-#define _R_F14 (_FPBASE+14)
-#define _R_F15 (_FPBASE+15)
-#define _R_F16 (_FPBASE+16)
-#define _R_F17 (_FPBASE+17)
-#define _R_F18 (_FPBASE+18)
-#define _R_F19 (_FPBASE+19)
-#define _R_F20 (_FPBASE+20)
-#define _R_F21 (_FPBASE+21)
-#define _R_F22 (_FPBASE+22)
-#define _R_F23 (_FPBASE+23)
-#define _R_F24 (_FPBASE+24)
-#define _R_F25 (_FPBASE+25)
-#define _R_F26 (_FPBASE+26)
-#define _R_F27 (_FPBASE+27)
-#define _R_F28 (_FPBASE+28)
-#define _R_F29 (_FPBASE+29)
-#define _R_F30 (_FPBASE+30)
-#define _R_F31 (_FPBASE+31)
+#define _FPBASE (_R_PC + 1)
+#define _R_F0 (_FPBASE+0)
+#define _R_F1 (_FPBASE+1)
+#define _R_F2 (_FPBASE+2)
+#define _R_F3 (_FPBASE+3)
+#define _R_F4 (_FPBASE+4)
+#define _R_F5 (_FPBASE+5)
+#define _R_F6 (_FPBASE+6)
+#define _R_F7 (_FPBASE+7)
+#define _R_F8 (_FPBASE+8)
+#define _R_F9 (_FPBASE+9)
+#define _R_F10 (_FPBASE+10)
+#define _R_F11 (_FPBASE+11)
+#define _R_F12 (_FPBASE+12)
+#define _R_F13 (_FPBASE+13)
+#define _R_F14 (_FPBASE+14)
+#define _R_F15 (_FPBASE+15)
+#define _R_F16 (_FPBASE+16)
+#define _R_F17 (_FPBASE+17)
+#define _R_F18 (_FPBASE+18)
+#define _R_F19 (_FPBASE+19)
+#define _R_F20 (_FPBASE+20)
+#define _R_F21 (_FPBASE+21)
+#define _R_F22 (_FPBASE+22)
+#define _R_F23 (_FPBASE+23)
+#define _R_F24 (_FPBASE+24)
+#define _R_F25 (_FPBASE+25)
+#define _R_F26 (_FPBASE+26)
+#define _R_F27 (_FPBASE+27)
+#define _R_F28 (_FPBASE+28)
+#define _R_F29 (_FPBASE+29)
+#define _R_F30 (_FPBASE+30)
+#define _R_F31 (_FPBASE+31)
#define _R_FSR (_FPBASE+32)
#define _R_DSPBASE (_R_FSR + 1)
-#define _R_MULLO1 (_R_DSPBASE + 0)
-#define _R_MULHI1 (_R_DSPBASE + 1)
-#define _R_MULLO2 (_R_DSPBASE + 2)
-#define _R_MULHI2 (_R_DSPBASE + 3)
-#define _R_MULLO3 (_R_DSPBASE + 4)
-#define _R_MULHI3 (_R_DSPBASE + 5)
-#define _R_DSPCTL (_R_DSPBASE + 6)
+#define _R_MULLO1 (_R_DSPBASE + 0)
+#define _R_MULHI1 (_R_DSPBASE + 1)
+#define _R_MULLO2 (_R_DSPBASE + 2)
+#define _R_MULHI2 (_R_DSPBASE + 3)
+#define _R_MULLO3 (_R_DSPBASE + 4)
+#define _R_MULHI3 (_R_DSPBASE + 5)
+#define _R_DSPCTL (_R_DSPBASE + 6)
Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.62 src/sys/arch/mips/include/vmparam.h:1.63
--- src/sys/arch/mips/include/vmparam.h:1.62 Sun May 5 18:13:16 2019
+++ src/sys/arch/mips/include/vmparam.h Sun Jul 26 08:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: vmparam.h,v 1.62 2019/05/05 18:13:16 christos Exp $ */
+/* $NetBSD: vmparam.h,v 1.63 2020/07/26 08:08:41 simonb Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -66,11 +66,11 @@
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)
-#define MIN_PAGE_SHIFT 12
+#define MIN_PAGE_SHIFT 12
#define MAX_PAGE_SHIFT 14
-#define MAX_PAGE_SIZE (1 << MAX_PAGE_SHIFT)
-#define MIN_PAGE_SIZE (1 << MIN_PAGE_SHIFT)
+#define MAX_PAGE_SIZE (1 << MAX_PAGE_SHIFT)
+#define MIN_PAGE_SIZE (1 << MIN_PAGE_SHIFT)
/*
* USRSTACK is the top (end) of the user stack.
@@ -147,7 +147,7 @@
* The default PTE number is enough to cover 8 disks * MAXBSIZE.
*/
#ifndef USRIOSIZE
-#define USRIOSIZE (MAXBSIZE/PAGE_SIZE * 8)
+#define USRIOSIZE (MAXBSIZE/PAGE_SIZE * 8)
#endif
/*
@@ -158,46 +158,46 @@
* user/kernel map constants
* These are negative addresses since MIPS addresses are signed.
*/
-#define VM_MIN_ADDRESS ((vaddr_t)0x00000000)
+#define VM_MIN_ADDRESS ((vaddr_t)0x00000000)
#ifdef _LP64
-#define MIPS_VM_MAXUSER_ADDRESS ((vaddr_t) 1L << 40)
+#define MIPS_VM_MAXUSER_ADDRESS ((vaddr_t) 1L << 40)
#ifdef ENABLE_MIPS_16KB_PAGE
-#define VM_MAXUSER_ADDRESS mips_vm_maxuser_address
+#define VM_MAXUSER_ADDRESS mips_vm_maxuser_address
#else
-#define VM_MAXUSER_ADDRESS MIPS_VM_MAXUSER_ADDRESS
+#define VM_MAXUSER_ADDRESS MIPS_VM_MAXUSER_ADDRESS
#endif
-#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS /* 0x0000010000000000 */
-#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) 3L << 62) /* 0xC000000000000000 */
-#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) -1L << 31) /* 0xFFFFFFFF80000000 */
+#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS /* 0x0000010000000000 */
+#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) 3L << 62) /* 0xC000000000000000 */
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) -1L << 31) /* 0xFFFFFFFF80000000 */
#else
-#define VM_MAXUSER_ADDRESS ((vaddr_t)-0x7fffffff-1)/* 0xFFFFFFFF80000000 */
-#define VM_MAX_ADDRESS ((vaddr_t)-0x7fffffff-1)/* 0xFFFFFFFF80000000 */
-#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)-0x40000000) /* 0xFFFFFFFFC0000000 */
+#define VM_MAXUSER_ADDRESS ((vaddr_t)-0x7fffffff-1)/* 0xFFFFFFFF80000000 */
+#define VM_MAX_ADDRESS ((vaddr_t)-0x7fffffff-1)/* 0xFFFFFFFF80000000 */
+#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)-0x40000000) /* 0xFFFFFFFFC0000000 */
#ifdef ENABLE_MIPS_TX3900
-#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x01000000) /* 0xFFFFFFFFFF000000 */
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x01000000) /* 0xFFFFFFFFFF000000 */
#else
-#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x00004000) /* 0xFFFFFFFFFFFFC000 */
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x00004000) /* 0xFFFFFFFFFFFFC000 */
#endif
#endif
-#define VM_MAXUSER_ADDRESS32 ((vaddr_t)(1UL << 31)) /* 0x0000000080000000 */
+#define VM_MAXUSER_ADDRESS32 ((vaddr_t)(1UL << 31)) /* 0x0000000080000000 */
/*
* The address to which unspecified mapping requests default
*/
-#define __USE_TOPDOWN_VM
+#define __USE_TOPDOWN_VM
-#define VM_DEFAULT_ADDRESS_TOPDOWN(da, sz) \
+#define VM_DEFAULT_ADDRESS_TOPDOWN(da, sz) \
trunc_page(USRSTACK - MAXSSIZ - (sz) - user_stack_guard_size)
-#define VM_DEFAULT_ADDRESS_BOTTOMUP(da, sz) \
+#define VM_DEFAULT_ADDRESS_BOTTOMUP(da, sz) \
round_page((vaddr_t)(da) + (vsize_t)maxdmap)
-#define VM_DEFAULT_ADDRESS32_TOPDOWN(da, sz) \
+#define VM_DEFAULT_ADDRESS32_TOPDOWN(da, sz) \
trunc_page(USRSTACK32 - MAXSSIZ32 - (sz) - user_stack_guard_size)
-#define VM_DEFAULT_ADDRESS32_BOTTOMUP(da, sz) \
+#define VM_DEFAULT_ADDRESS32_BOTTOMUP(da, sz) \
round_page((vaddr_t)(da) + (vsize_t)MAXDSIZ32)
/* virtual sizes (bytes) for various kernel submaps */
-#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
+#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
/* VM_PHYSSEG_MAX defined by platform-dependent code. */
#define VM_PHYSSEG_STRAT VM_PSTRAT_BSEARCH
@@ -205,8 +205,8 @@
#ifndef VM_NFREELIST
#define VM_NFREELIST 16 /* 16 distinct memory segments */
-#define VM_FREELIST_DEFAULT 0
-#define VM_FREELIST_MAX 1
+#define VM_FREELIST_DEFAULT 0
+#define VM_FREELIST_MAX 1
#endif
#ifdef _KERNEL
