Module Name: src
Committed By: simonb
Date: Tue Aug 4 01:59:46 UTC 2020
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_corereg.h
Log Message:
Add some CvmCtl bits from newer cnMIPS cores.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_corereg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/dev/octeon_corereg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.4 src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.4 Sun Jul 26 07:46:21 2020
+++ src/sys/arch/mips/cavium/dev/octeon_corereg.h Tue Aug 4 01:59:46 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_corereg.h,v 1.4 2020/07/26 07:46:21 simonb Exp $ */
+/* $NetBSD: octeon_corereg.h,v 1.5 2020/08/04 01:59:46 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -87,8 +87,17 @@
#define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001)
/* CvmCtl Register */
+/* CVMCTL_STEPRATE to CVMCTL_TLBBRFTDIS are available on cnMIPS III cores */
-#define CP0_CVMCTL_XXX_63_32 UINT64_C(0xffffffff00000000)
+#define CP0_CVMCTL_XXX_63_43 UINT64_C(0xfffff80000000000)
+#define CP0_CVMCTL_STEPRATE UINT64_C(0x0000078000000000)
+#define CP0_CVMCTL_ZUC UINT64_C(0x0000004000000000)
+#define CP0_CVMCTL_CAMELLIA UINT64_C(0x0000002000000000)
+#define CP0_CVMCTL_USEMAK UINT64_C(0x0000001000000000)
+#define CP0_CVMCTL_SMS4 UINT64_C(0x0000000800000000)
+#define CP0_CVMCTL_DISABLEPAUSE UINT64_C(0x0000000400000000)
+#define CP0_CVMCTL_SNOW3G UINT64_C(0x0000000200000000)
+#define CP0_CVMCTL_TLBBRFTDIS UINT64_C(0x0000000100000000)
#define CP0_CVMCTL_FUSE_STARTBIT UINT64_C(0x0000000080000000)
#define CP0_CVMCTL_XXX_30 UINT64_C(0x0000000040000000)
#define CP0_CVMCTL_KASUMI UINT64_C(0x0000000020000000)
