Module Name: src
Committed By: martin
Date: Wed Aug 5 15:14:18 UTC 2020
Modified Files:
src/sys/dev/mii [netbsd-9]: igphy.c igphyreg.h makphy.c makphyreg.h
src/sys/dev/pci [netbsd-9]: if_wm.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1040):
sys/dev/mii/igphy.c: revision 1.35
sys/dev/mii/igphy.c: revision 1.36
sys/dev/mii/igphyreg.h: revision 1.12
sys/dev/mii/igphyreg.h: revision 1.13
sys/dev/mii/makphyreg.h: revision 1.11
sys/dev/pci/if_wm.c: revision 1.682
sys/dev/pci/if_wm.c: revision 1.683
sys/dev/pci/if_wm.c: revision 1.684
sys/dev/pci/if_wm.c: revision 1.685
sys/dev/mii/makphy.c: revision 1.66
s/MII_IGPHY_/IGPHY_/. No functional change.
Rename PSSR_* to MAKPHY_PSSR_* and IGPHY_PSSR_* to avoid conflict.
No functional change.
Setup PCS and SGMII for SFP correctly. It still doesn't support SFP
insertion/removal.
Copper:
wm2: SGMII(SFP)
wm2: 0x1043c440<SPI,IOH_VALID,PCIE,SGMII,NEWQUEUE,ASF_FIRM,EEE,SFP>
makphy0 at wm2 phy 6: Marvell 88E1111 Gigabit PHY, rev. 1
Fiber:
wm3: SERDES(SFP)
wm3: 0x10034440<SPI,IOH_VALID,PCIE,NEWQUEUE,ASF_FIRM,SFP>
wm3: 1000baseSX, 1000baseSX-FDX, auto
Explicitly cast from uint16_t to uint32_t before shifting 16bit left
when printing Image Unique ID. Found by kUBSan.
Set if_baudrate for non-MII device. Before this commit, it was 0.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.31.4.1 src/sys/dev/mii/igphy.c
cvs rdiff -u -r1.11 -r1.11.4.1 src/sys/dev/mii/igphyreg.h
cvs rdiff -u -r1.60.2.1 -r1.60.2.2 src/sys/dev/mii/makphy.c
cvs rdiff -u -r1.9.6.1 -r1.9.6.2 src/sys/dev/mii/makphyreg.h
cvs rdiff -u -r1.645.2.5 -r1.645.2.6 src/sys/dev/pci/if_wm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/igphy.c
diff -u src/sys/dev/mii/igphy.c:1.31 src/sys/dev/mii/igphy.c:1.31.4.1
--- src/sys/dev/mii/igphy.c:1.31 Mon Mar 25 07:34:13 2019
+++ src/sys/dev/mii/igphy.c Wed Aug 5 15:14:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: igphy.c,v 1.31 2019/03/25 07:34:13 msaitoh Exp $ */
+/* $NetBSD: igphy.c,v 1.31.4.1 2020/08/05 15:14:18 martin Exp $ */
/*
* The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.31 2019/03/25 07:34:13 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.31.4.1 2020/08/05 15:14:18 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_mii.h"
@@ -270,7 +270,7 @@ igphy_load_dspcode(struct mii_softc *sc)
delay(20000);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x0140);
delay(5000);
@@ -278,7 +278,7 @@ igphy_load_dspcode(struct mii_softc *sc)
for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
IGPHY_WRITE(sc, code[i].reg, code[i].val);
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
PHY_WRITE(sc, 0x0000, 0x3300);
delay(20000);
@@ -323,9 +323,9 @@ igphy_reset(struct mii_softc *sc)
}
if (igsc->sc_mactype == WM_T_82547) {
- IGPHY_READ(sc, MII_IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
+ IGPHY_READ(sc, IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
if ((fused & ANALOG_SPARE_FUSE_ENABLED) == 0) {
- IGPHY_READ(sc, MII_IGPHY_ANALOG_FUSE_STATUS, &fused);
+ IGPHY_READ(sc, IGPHY_ANALOG_FUSE_STATUS, &fused);
fine = fused & ANALOG_FUSE_FINE_MASK;
coarse = fused & ANALOG_FUSE_COARSE_MASK;
@@ -340,12 +340,12 @@ igphy_reset(struct mii_softc *sc)
(fine & ANALOG_FUSE_FINE_MASK) |
(coarse & ANALOG_FUSE_COARSE_MASK);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_CONTROL, fused);
- IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_BYPASS,
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_CONTROL, fused);
+ IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_BYPASS,
ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
- PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+ PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
}
@@ -377,14 +377,14 @@ igphy_service(struct mii_softc *sc, stru
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
- PHY_READ(sc, MII_IGPHY_PORT_CTRL, ®);
+ PHY_READ(sc, IGPHY_PORT_CTRL, ®);
if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
reg |= PSCR_AUTO_MDIX;
reg &= ~PSCR_FORCE_MDI_MDIX;
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
} else {
reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);
- PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+ PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
}
mii_phy_setmedia(sc);
@@ -425,9 +425,9 @@ igphy_status(struct mii_softc *sc)
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
- PHY_READ(sc, MII_IGPHY_PORT_STATUS, &pssr);
+ PHY_READ(sc, IGPHY_PORT_STATUS, &pssr);
- if (pssr & PSSR_LINK_UP)
+ if (pssr & IGPHY_PSSR_LINK_UP)
mii->mii_media_status |= IFM_ACTIVE;
PHY_READ(sc, MII_BMCR, &bmcr);
@@ -449,19 +449,19 @@ igphy_status(struct mii_softc *sc)
mii->mii_media_active |= IFM_NONE;
return;
}
- switch (pssr & PSSR_SPEED_MASK) {
- case PSSR_SPEED_1000MBPS:
+ switch (pssr & IGPHY_PSSR_SPEED_MASK) {
+ case IGPHY_PSSR_SPEED_1000MBPS:
mii->mii_media_active |= IFM_1000_T;
PHY_READ(sc, MII_100T2SR, >sr);
if (gtsr & GTSR_MS_RES)
mii->mii_media_active |= IFM_ETH_MASTER;
break;
- case PSSR_SPEED_100MBPS:
+ case IGPHY_PSSR_SPEED_100MBPS:
mii->mii_media_active |= IFM_100_TX;
break;
- case PSSR_SPEED_10MBPS:
+ case IGPHY_PSSR_SPEED_10MBPS:
mii->mii_media_active |= IFM_10_T;
break;
@@ -471,7 +471,7 @@ igphy_status(struct mii_softc *sc)
return;
}
- if (pssr & PSSR_FULL_DUPLEX)
+ if (pssr & IGPHY_PSSR_FULL_DUPLEX)
mii->mii_media_active |=
IFM_FDX | mii_phy_flowstatus(sc);
else
Index: src/sys/dev/mii/igphyreg.h
diff -u src/sys/dev/mii/igphyreg.h:1.11 src/sys/dev/mii/igphyreg.h:1.11.4.1
--- src/sys/dev/mii/igphyreg.h:1.11 Tue Jan 22 03:42:27 2019
+++ src/sys/dev/mii/igphyreg.h Wed Aug 5 15:14:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: igphyreg.h,v 1.11 2019/01/22 03:42:27 msaitoh Exp $ */
+/* $NetBSD: igphyreg.h,v 1.11.4.1 2020/08/05 15:14:18 martin Exp $ */
/*******************************************************************************
@@ -43,7 +43,7 @@
*/
/* IGP01E1000 Specific Port Config Register - R/W */
-#define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
+#define IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
#define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define PSCFR_PRE_EN 0x0020
#define PSCFR_SMART_SPEED 0x0080
@@ -52,22 +52,22 @@
#define PSCFR_DISABLE_TRANSMIT 0x2000
/* IGP01E1000 Specific Port Status Register - R/O */
-#define MII_IGPHY_PORT_STATUS 0x11
-#define PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
-#define PSSR_POLARITY_REVERSED 0x0002
-#define PSSR_CABLE_LENGTH 0x007C
-#define PSSR_FULL_DUPLEX 0x0200
-#define PSSR_LINK_UP 0x0400
-#define PSSR_MDIX 0x0800
-#define PSSR_SPEED_MASK 0xC000 /* speed bits mask */
-#define PSSR_SPEED_10MBPS 0x4000
-#define PSSR_SPEED_100MBPS 0x8000
-#define PSSR_SPEED_1000MBPS 0xC000
-#define PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
-#define PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
+#define IGPHY_PORT_STATUS 0x11
+#define IGPHY_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
+#define IGPHY_PSSR_POLARITY_REVERSED 0x0002
+#define IGPHY_PSSR_CABLE_LENGTH 0x007C
+#define IGPHY_PSSR_FULL_DUPLEX 0x0200
+#define IGPHY_PSSR_LINK_UP 0x0400
+#define IGPHY_PSSR_MDIX 0x0800
+#define IGPHY_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
+#define IGPHY_PSSR_SPEED_10MBPS 0x4000
+#define IGPHY_PSSR_SPEED_100MBPS 0x8000
+#define IGPHY_PSSR_SPEED_1000MBPS 0xC000
+#define IGPHY_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
+#define IGPHY_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
/* IGP01E1000 Specific Port Control Register - R/W */
-#define MII_IGPHY_PORT_CTRL 0x12
+#define IGPHY_PORT_CTRL 0x12
#define PSCR_TP_LOOPBACK 0x0010
#define PSCR_CORRECT_NC_SCMBLR 0x0200
#define PSCR_TEN_CRS_SELECT 0x0400
@@ -76,7 +76,7 @@
#define PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
/* IGP01E1000 Specific Port Link Health Register */
-#define MII_IGPHY_LINK_HEALTH 0x13
+#define IGPHY_LINK_HEALTH 0x13
#define PLHR_VALID_CHANNEL_A 0x0001
#define PLHR_VALID_CHANNEL_B 0x0002
#define PLHR_VALID_CHANNEL_C 0x0004
@@ -96,61 +96,61 @@
#define GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Channel Quality Register */
-#define MII_IGPHY_CHANNEL_QUALITY 0x15
+#define IGPHY_CHANNEL_QUALITY 0x15
#define MSE_CHANNEL_A 0x000F
#define MSE_CHANNEL_B 0x00F0
#define MSE_CHANNEL_C 0x0F00
#define MSE_CHANNEL_D 0xF000
/* IGP01E1000 Power Management */
-#define MII_IGPHY_POWER_MGMT 0x19
+#define IGPHY_POWER_MGMT 0x19
#define PMR_SPD_EN 0x0001
#define PMR_D0_LPLU 0x0002
#define PMR_D3_LPLU 0x0004
#define PMR_DIS_1000 0x0040
-#define MII_IGPHY_PAGE_SELECT 0x1F
+#define IGPHY_PAGE_SELECT 0x1F
#define IGPHY_MAXREGADDR 0x1F
#define IGPHY_PAGEMASK (~IGPHY_MAXREGADDR)
/* IGP01E1000 AGC Registers - stores the cable length values*/
-#define MII_IGPHY_AGC_A 0x1172
-#define MII_IGPHY_AGC_PARAM_A 0x1171
-#define MII_IGPHY_AGC_B 0x1272
-#define MII_IGPHY_AGC_PARAM_B 0x1271
-#define MII_IGPHY_AGC_C 0x1472
-#define MII_IGPHY_AGC_PARAM_C 0x1471
-#define MII_IGPHY_AGC_D 0x1872
-#define MII_IGPHY_AGC_PARAM_D 0x1871
+#define IGPHY_AGC_A 0x1172
+#define IGPHY_AGC_PARAM_A 0x1171
+#define IGPHY_AGC_B 0x1272
+#define IGPHY_AGC_PARAM_B 0x1271
+#define IGPHY_AGC_C 0x1472
+#define IGPHY_AGC_PARAM_C 0x1471
+#define IGPHY_AGC_D 0x1872
+#define IGPHY_AGC_PARAM_D 0x1871
#define AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
#define AGC_LENGTH_TABLE_SIZE 128
#define AGC_RANGE 10
/* IGP01E1000 DSP Reset Register */
-#define MII_IGPHY_DSP_RESET 0x1F33
-#define MII_IGPHY_DSP_SET 0x1F71
-#define MII_IGPHY_DSP_FFE 0x1F35
-#define MII_IGPHY_CHANNEL_NUM 4
-#define MII_IGPHY_EDAC_MU_INDEX 0xC000
-#define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
-#define MII_IGPHY_ANALOG_TX_STATE 0x2890
-#define MII_IGPHY_ANALOG_CLASS_A 0x2000
-#define MII_IGPHY_FORCE_ANALOG_ENABLE 0x0004
-#define MII_IGPHY_DSP_FFE_CM_CP 0x0069
-#define MII_IGPHY_DSP_FFE_DEFAULT 0x002A
+#define IGPHY_DSP_RESET 0x1F33
+#define IGPHY_DSP_SET 0x1F71
+#define IGPHY_DSP_FFE 0x1F35
+#define IGPHY_CHANNEL_NUM 4
+#define IGPHY_EDAC_MU_INDEX 0xC000
+#define IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
+#define IGPHY_ANALOG_TX_STATE 0x2890
+#define IGPHY_ANALOG_CLASS_A 0x2000
+#define IGPHY_FORCE_ANALOG_ENABLE 0x0004
+#define IGPHY_DSP_FFE_CM_CP 0x0069
+#define IGPHY_DSP_FFE_DEFAULT 0x002A
/* IGP01E1000 PCS Initialization register - stores the polarity status */
-#define MII_IGPHY_PCS_INIT_REG 0x00B4
-#define MII_IGPHY_PCS_CTRL_REG 0x00B5
+#define IGPHY_PCS_INIT_REG 0x00B4
+#define IGPHY_PCS_CTRL_REG 0x00B5
-#define MII_IGPHY_ANALOG_REGS_PAGE 0x20C0
+#define IGPHY_ANALOG_REGS_PAGE 0x20C0
#define PHY_POLARITY_MASK 0x0078
/* IGP01E1000 Analog Register */
-#define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
-#define MII_IGPHY_ANALOG_FUSE_STATUS 0x20D0
-#define MII_IGPHY_ANALOG_FUSE_CONTROL 0x20DC
-#define MII_IGPHY_ANALOG_FUSE_BYPASS 0x20DE
+#define IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGPHY_ANALOG_FUSE_STATUS 0x20D0
+#define IGPHY_ANALOG_FUSE_CONTROL 0x20DC
+#define IGPHY_ANALOG_FUSE_BYPASS 0x20DE
#define ANALOG_FUSE_POLY_MASK 0xF000
#define ANALOG_FUSE_FINE_MASK 0x0F80
#define ANALOG_FUSE_COARSE_MASK 0x0070
@@ -180,7 +180,7 @@ IGPHY_READ(struct mii_softc *sc, int reg
{
int rv;
- if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+ if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
return rv;
return PHY_READ(sc, reg & 0x1f, val);
}
@@ -189,7 +189,7 @@ IGPHY_WRITE(struct mii_softc *sc, int re
{
int rv;
- if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+ if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
return rv;
return PHY_WRITE(sc, reg & 0x1f, val);
Index: src/sys/dev/mii/makphy.c
diff -u src/sys/dev/mii/makphy.c:1.60.2.1 src/sys/dev/mii/makphy.c:1.60.2.2
--- src/sys/dev/mii/makphy.c:1.60.2.1 Tue Jan 28 11:04:14 2020
+++ src/sys/dev/mii/makphy.c Wed Aug 5 15:14:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: makphy.c,v 1.60.2.1 2020/01/28 11:04:14 martin Exp $ */
+/* $NetBSD: makphy.c,v 1.60.2.2 2020/08/05 15:14:18 martin Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -59,7 +59,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.60.2.1 2020/01/28 11:04:14 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.60.2.2 2020/08/05 15:14:18 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -428,7 +428,7 @@ makphy_status(struct mii_softc *sc)
/* XXX FIXME: Use different page for Fiber on newer chips */
PHY_READ(sc, MAKPHY_PSSR, &pssr);
- if (pssr & PSSR_LINK)
+ if (pssr & MAKPHY_PSSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
if (bmcr & BMCR_LOOP)
@@ -445,13 +445,13 @@ makphy_status(struct mii_softc *sc)
* Check Speed and Duplex Resolved bit.
* Note that this bit is always 1 when autonego is not enabled.
*/
- if (!(pssr & PSSR_RESOLVED)) {
+ if (!(pssr & MAKPHY_PSSR_RESOLVED)) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
} else {
- if ((pssr & PSSR_LINK) == 0) {
+ if ((pssr & MAKPHY_PSSR_LINK) == 0) {
mii->mii_media_active |= IFM_NONE;
return;
}
@@ -479,10 +479,10 @@ makphy_status(struct mii_softc *sc)
/* Fiber/Copper auto select mode */
PHY_READ(sc, MAKPHY_PSSR, &pssr);
- if ((pssr & PSSR_RESOLUTION_FIBER) == 0)
+ if ((pssr & MAKPHY_PSSR_RESOLUTION_FIBER) == 0)
goto copper;
- switch (PSSR_SPEED_get(pssr)) {
+ switch (MAKPHY_PSSR_SPEED_get(pssr)) {
case SPEED_1000:
mii->mii_media_active |= IFM_1000_SX;
break;
@@ -496,7 +496,7 @@ makphy_status(struct mii_softc *sc)
}
} else {
copper:
- switch (PSSR_SPEED_get(pssr)) {
+ switch (MAKPHY_PSSR_SPEED_get(pssr)) {
case SPEED_1000:
mii->mii_media_active |= IFM_1000_T;
break;
@@ -513,7 +513,7 @@ copper:
}
}
- if (pssr & PSSR_DUPLEX)
+ if (pssr & MAKPHY_PSSR_DUPLEX)
mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
Index: src/sys/dev/mii/makphyreg.h
diff -u src/sys/dev/mii/makphyreg.h:1.9.6.1 src/sys/dev/mii/makphyreg.h:1.9.6.2
--- src/sys/dev/mii/makphyreg.h:1.9.6.1 Tue Jan 28 11:04:14 2020
+++ src/sys/dev/mii/makphyreg.h Wed Aug 5 15:14:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: makphyreg.h,v 1.9.6.1 2020/01/28 11:04:14 martin Exp $ */
+/* $NetBSD: makphyreg.h,v 1.9.6.2 2020/08/05 15:14:18 martin Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -92,15 +92,15 @@
#define MSCR_ENHANCED_SGMII 0x0004 /* Enhanced SGMII */
#define MAKPHY_PSSR 0x11 /* PHY specific status register */
-#define PSSR_JABBER (1U << 0) /* jabber indication */
-#define PSSR_POLARITY (1U << 1) /* polarity indiciation */
-#define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */
-#define PSSR_CABLE_LENGTH_get(x) (((x) >> 7) & 0x3)
-#define PSSR_LINK (1U << 10) /* link indication */
-#define PSSR_RESOLVED (1U << 11) /* speed and duplex resolved */
-#define PSSR_PAGE_RECEIVED (1U << 12) /* page received */
-#define PSSR_DUPLEX (1U << 13) /* 1 = FDX */
-#define PSSR_SPEED_get(x) (((x) >> 14) & 0x3)
+#define MAKPHY_PSSR_JABBER (1U << 0) /* jabber indication */
+#define MAKPHY_PSSR_POLARITY (1U << 1) /* polarity indiciation */
+#define MAKPHY_PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */
+#define MAKPHY_PSSR_CABLE_LENGTH_get(x) (((x) >> 7) & 0x3)
+#define MAKPHY_PSSR_LINK (1U << 10) /* link indication */
+#define MAKPHY_PSSR_RESOLVED (1U << 11) /* speed and duplex resolved */
+#define MAKPHY_PSSR_PAGE_RECEIVED (1U << 12) /* page received */
+#define MAKPHY_PSSR_DUPLEX (1U << 13) /* 1 = FDX */
+#define MAKPHY_PSSR_SPEED_get(x) (((x) >> 14) & 0x3)
#define SPEED_10 0
#define SPEED_100 1
@@ -108,10 +108,10 @@
#define SPEED_reserved 3
/* For 88E1112 */
-#define PSSR_RESOLUTION_FIBER (1U << 7) /*
- * Fiber/Copper resolution
- * 1 = Fiber, 0 = Copper
- */
+#define MAKPHY_PSSR_RESOLUTION_FIBER (1U << 7) /*
+ * Fiber/Copper resolution
+ * 1 = Fiber, 0 = Copper
+ */
#define MAKPHY_IE 0x12 /* Interrupt enable */
#define IE_JABBER (1U << 0) /* jabber indication */
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.645.2.5 src/sys/dev/pci/if_wm.c:1.645.2.6
--- src/sys/dev/pci/if_wm.c:1.645.2.5 Fri Jul 10 10:45:56 2020
+++ src/sys/dev/pci/if_wm.c Wed Aug 5 15:14:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.645.2.5 2020/07/10 10:45:56 martin Exp $ */
+/* $NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.5 2020/07/10 10:45:56 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -139,6 +139,7 @@ __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.
#include <dev/mii/igphyvar.h>
#include <dev/mii/inbmphyreg.h>
#include <dev/mii/ihphyreg.h>
+#include <dev/mii/makphyreg.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
@@ -886,6 +887,7 @@ static int wm_read_emi_reg_locked(device
static int wm_write_emi_reg_locked(device_t, int, uint16_t);
/* SGMII */
static bool wm_sgmii_uses_mdio(struct wm_softc *);
+static void wm_sgmii_sfp_preconfig(struct wm_softc *);
static int wm_sgmii_readreg(device_t, int, int, uint16_t *);
static int wm_sgmii_readreg_locked(device_t, int, int, uint16_t *);
static int wm_sgmii_writereg(device_t, int, int, uint16_t);
@@ -4316,7 +4318,7 @@ wm_init_lcd_from_nvm(struct wm_softc *sc
if (wm_nvm_read(sc, (word_addr + i * 2 + 1), 1, ®_addr) !=0)
goto release;
- if (reg_addr == MII_IGPHY_PAGE_SELECT)
+ if (reg_addr == IGPHY_PAGE_SELECT)
phy_page = reg_data;
reg_addr &= IGPHY_MAXREGADDR;
@@ -10416,7 +10418,6 @@ wm_get_phy_id_82575(struct wm_softc *sc)
return phyid;
}
-
/*
* wm_gmii_mediainit:
*
@@ -10466,6 +10467,9 @@ wm_gmii_mediainit(struct wm_softc *sc, p
ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
wm_gmii_mediastatus);
+ /* Setup internal SGMII PHY for SFP */
+ wm_sgmii_sfp_preconfig(sc);
+
if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
|| (sc->sc_type == WM_T_82580)
|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
@@ -10909,7 +10913,7 @@ wm_gmii_i82544_readreg_locked(device_t d
case WMPHY_IGP_2:
case WMPHY_IGP_3:
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, reg);
+ IGPHY_PAGE_SELECT, reg);
if (rv != 0)
return rv;
break;
@@ -10959,7 +10963,7 @@ wm_gmii_i82544_writereg_locked(device_t
case WMPHY_IGP_2:
case WMPHY_IGP_3:
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, reg);
+ IGPHY_PAGE_SELECT, reg);
if (rv != 0)
return rv;
break;
@@ -11124,7 +11128,7 @@ wm_gmii_bm_readreg(device_t dev, int phy
if ((phy == 1) && (sc->sc_type != WM_T_82574)
&& (sc->sc_type != WM_T_82583))
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
else
rv = wm_gmii_mdic_writereg(dev, phy,
BME1000_PHY_PAGE_SELECT, page);
@@ -11171,7 +11175,7 @@ wm_gmii_bm_writereg(device_t dev, int ph
if ((phy == 1) && (sc->sc_type != WM_T_82574)
&& (sc->sc_type != WM_T_82583))
rv = wm_gmii_mdic_writereg(dev, phy,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
else
rv = wm_gmii_mdic_writereg(dev, phy,
BME1000_PHY_PAGE_SELECT, page);
@@ -11209,7 +11213,7 @@ wm_enable_phy_wakeup_reg_access_bm(devic
/* All page select, port ctrl and wakeup registers use phy address 1 */
/* Select Port Control Registers page */
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_PORT_CTRL_PAGE << IGP3_PAGE_SHIFT);
if (rv != 0)
return rv;
@@ -11232,7 +11236,7 @@ wm_enable_phy_wakeup_reg_access_bm(devic
/* Select Host Wakeup Registers page - caller now able to write
* registers on the Wakeup registers page
*/
- return wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ return wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_WUC_PAGE << IGP3_PAGE_SHIFT);
}
@@ -11258,7 +11262,7 @@ wm_disable_phy_wakeup_reg_access_bm(devi
return -1;
/* Select Port Control Registers page */
- wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
BM_PORT_CTRL_PAGE << IGP3_PAGE_SHIFT);
/* Restore 769.17 to its original value */
@@ -11405,7 +11409,7 @@ wm_gmii_hv_readreg_locked(device_t dev,
page = 0;
if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
page << BME1000_PAGE_SHIFT);
if (rv != 0)
return rv;
@@ -11491,7 +11495,7 @@ wm_gmii_hv_writereg_locked(device_t dev,
if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
rv = wm_gmii_mdic_writereg(dev, 1,
- MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
+ IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
if (rv != 0)
return rv;
}
@@ -11852,6 +11856,38 @@ wm_sgmii_uses_mdio(struct wm_softc *sc)
return ismdio;
}
+/* Setup internal SGMII PHY for SFP */
+static void
+wm_sgmii_sfp_preconfig(struct wm_softc *sc)
+{
+ uint16_t id1, id2, phyreg;
+ int i, rv;
+
+ if (((sc->sc_flags & WM_F_SGMII) == 0)
+ || ((sc->sc_flags & WM_F_SFP) == 0))
+ return;
+
+ for (i = 0; i < MII_NPHY; i++) {
+ sc->phy.no_errprint = true;
+ rv = sc->phy.readreg_locked(sc->sc_dev, i, MII_PHYIDR1, &id1);
+ if (rv != 0)
+ continue;
+ rv = sc->phy.readreg_locked(sc->sc_dev, i, MII_PHYIDR2, &id2);
+ if (rv != 0)
+ continue;
+ if (MII_OUI(id1, id2) != MII_OUI_xxMARVELL)
+ continue;
+ sc->phy.no_errprint = false;
+
+ sc->phy.readreg_locked(sc->sc_dev, i, MAKPHY_ESSR, &phyreg);
+ phyreg &= ~(ESSR_SER_ANEG_BYPASS | ESSR_HWCFG_MODE);
+ phyreg |= ESSR_SGMII_WOC_COPPER;
+ sc->phy.writereg_locked(sc->sc_dev, i, MAKPHY_ESSR, phyreg);
+ break;
+ }
+
+}
+
/*
* wm_sgmii_readreg: [mii interface function]
*
@@ -12009,6 +12045,7 @@ wm_tbi_mediainit(struct wm_softc *sc)
sc->sc_mii.mii_ifp = ifp;
sc->sc_ethercom.ec_mii = &sc->sc_mii;
+ ifp->if_baudrate = IF_Gbps(1);
if (((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211))
&& (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
@@ -12438,9 +12475,14 @@ wm_serdes_mediachange(struct ifnet *ifp)
sc->sc_ctrl |= CTRL_SLU;
- if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
+ if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1);
+ reg = CSR_READ(sc, WMREG_CONNSW);
+ reg |= CONNSW_ENRGSRC;
+ CSR_WRITE(sc, WMREG_CONNSW, reg);
+ }
+
pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) {
case CTRL_EXT_LINK_MODE_SGMII:
@@ -12536,6 +12578,7 @@ wm_serdes_mediastatus(struct ifnet *ifp,
break;
}
}
+ ifp->if_baudrate = ifmedia_baudrate(ifmr->ifm_active);
if ((reg & PCS_LSTS_FDX) != 0)
ifmr->ifm_active |= IFM_FDX;
else
@@ -13930,7 +13973,8 @@ printver:
}
if (have_uid && (wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0) == 0))
- aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0);
+ aprint_verbose(", Image Unique ID %08x",
+ ((uint32_t)uid1 << 16) | uid0);
}
/*
@@ -15493,9 +15537,9 @@ wm_lplu_d0_disable(struct wm_softc *sc)
case WM_T_82573:
case WM_T_82575:
case WM_T_82576:
- mii->mii_readreg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, &phyval);
+ mii->mii_readreg(sc->sc_dev, 1, IGPHY_POWER_MGMT, &phyval);
phyval &= ~PMR_D0_LPLU;
- mii->mii_writereg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, phyval);
+ mii->mii_writereg(sc->sc_dev, 1, IGPHY_POWER_MGMT, phyval);
break;
case WM_T_82580:
case WM_T_I350:
@@ -15821,7 +15865,7 @@ wm_hv_phy_workarounds_ich8lan(struct wm_
/* Select page 0 */
if ((rv = sc->phy.acquire(sc)) != 0)
return rv;
- rv = wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT, 0);
+ rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT, 0);
sc->phy.release(sc);
if (rv != 0)
return rv;
