Module Name: src
Committed By: martin
Date: Tue Aug 18 09:29:52 UTC 2020
Modified Files:
src/sys/dev/nvmm [netbsd-9]: nvmm.c nvmm.h nvmm_internal.h
src/sys/dev/nvmm/x86 [netbsd-9]: nvmm_x86.c nvmm_x86_svm.c
nvmm_x86_vmx.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #1055):
sys/dev/nvmm/nvmm.h: revision 1.13
sys/dev/nvmm/nvmm.h: revision 1.14
sys/dev/nvmm/nvmm.c: revision 1.33
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.67
sys/dev/nvmm/nvmm_internal.h: revision 1.17
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.67
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.10
Put the few x86-specific structures under #ifdef __x86_64__, for clarity.
Make it easier to understand what's going on, no functional change.
Add new field definitions.
Add new field definitions, and intercept everything, for future-proofness.
Add CTASSERT.
To generate a diff of this commit:
cvs rdiff -u -r1.22.2.5 -r1.22.2.6 src/sys/dev/nvmm/nvmm.c
cvs rdiff -u -r1.10.4.1 -r1.10.4.2 src/sys/dev/nvmm/nvmm.h
cvs rdiff -u -r1.12.2.4 -r1.12.2.5 src/sys/dev/nvmm/nvmm_internal.h
cvs rdiff -u -r1.7.4.2 -r1.7.4.3 src/sys/dev/nvmm/x86/nvmm_x86.c
cvs rdiff -u -r1.46.4.7 -r1.46.4.8 src/sys/dev/nvmm/x86/nvmm_x86_svm.c
cvs rdiff -u -r1.36.2.9 -r1.36.2.10 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/nvmm/nvmm.c
diff -u src/sys/dev/nvmm/nvmm.c:1.22.2.5 src/sys/dev/nvmm/nvmm.c:1.22.2.6
--- src/sys/dev/nvmm/nvmm.c:1.22.2.5 Sun Aug 2 08:49:08 2020
+++ src/sys/dev/nvmm/nvmm.c Tue Aug 18 09:29:52 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm.c,v 1.22.2.5 2020/08/02 08:49:08 martin Exp $ */
+/* $NetBSD: nvmm.c,v 1.22.2.6 2020/08/18 09:29:52 martin Exp $ */
/*
* Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm.c,v 1.22.2.5 2020/08/02 08:49:08 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm.c,v 1.22.2.6 2020/08/18 09:29:52 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -59,8 +59,10 @@ static struct nvmm_machine machines[NVMM
static volatile unsigned int nmachines __cacheline_aligned;
static const struct nvmm_impl *nvmm_impl_list[] = {
+#if defined(__x86_64__)
&nvmm_x86_svm, /* x86 AMD SVM */
&nvmm_x86_vmx /* x86 Intel VMX */
+#endif
};
static const struct nvmm_impl *nvmm_impl = NULL;
Index: src/sys/dev/nvmm/nvmm.h
diff -u src/sys/dev/nvmm/nvmm.h:1.10.4.1 src/sys/dev/nvmm/nvmm.h:1.10.4.2
--- src/sys/dev/nvmm/nvmm.h:1.10.4.1 Sun Nov 10 12:58:30 2019
+++ src/sys/dev/nvmm/nvmm.h Tue Aug 18 09:29:52 2020
@@ -1,7 +1,7 @@
-/* $NetBSD: nvmm.h,v 1.10.4.1 2019/11/10 12:58:30 martin Exp $ */
+/* $NetBSD: nvmm.h,v 1.10.4.2 2020/08/18 09:29:52 martin Exp $ */
/*
- * Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
+ * Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
@@ -44,7 +44,7 @@ typedef uint64_t gvaddr_t;
typedef uint32_t nvmm_machid_t;
typedef uint32_t nvmm_cpuid_t;
-#ifdef __x86_64__
+#if defined(__x86_64__)
#include <dev/nvmm/x86/nvmm_x86.h>
#endif
@@ -96,4 +96,9 @@ struct nvmm_comm_page {
#define NVMM_COMM_CPUID(off) \
((off >> 12) & 0xFF)
+#ifdef _KERNEL
+/* At most one page, for the NVMM_COMM_* macros. */
+CTASSERT(sizeof(struct nvmm_comm_page) <= PAGE_SIZE);
+#endif
+
#endif
Index: src/sys/dev/nvmm/nvmm_internal.h
diff -u src/sys/dev/nvmm/nvmm_internal.h:1.12.2.4 src/sys/dev/nvmm/nvmm_internal.h:1.12.2.5
--- src/sys/dev/nvmm/nvmm_internal.h:1.12.2.4 Sun Aug 2 11:19:09 2020
+++ src/sys/dev/nvmm/nvmm_internal.h Tue Aug 18 09:29:52 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_internal.h,v 1.12.2.4 2020/08/02 11:19:09 martin Exp $ */
+/* $NetBSD: nvmm_internal.h,v 1.12.2.5 2020/08/18 09:29:52 martin Exp $ */
/*
* Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
@@ -119,8 +119,10 @@ struct nvmm_impl {
struct nvmm_vcpu_exit *);
};
+#if defined(__x86_64__)
extern const struct nvmm_impl nvmm_x86_svm;
extern const struct nvmm_impl nvmm_x86_vmx;
+#endif
static inline bool
nvmm_return_needed(void)
Index: src/sys/dev/nvmm/x86/nvmm_x86.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.2 src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.3
--- src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.2 Thu May 21 10:52:58 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86.c Tue Aug 18 09:29:52 2020
@@ -1,7 +1,7 @@
-/* $NetBSD: nvmm_x86.c,v 1.7.4.2 2020/05/21 10:52:58 martin Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.7.4.3 2020/08/18 09:29:52 martin Exp $ */
/*
- * Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
+ * Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.2 2020/05/21 10:52:58 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.3 2020/08/18 09:29:52 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -233,85 +233,191 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
.eax = ~0,
.ebx = ~0,
.ecx =
- /* Excluded: MONITOR, VMX, SMX, EST, TM2, PDCM, PCID, DCA, X2APIC,
- * DEADLINE, RAZ. */
- CPUID2_SSE3 | CPUID2_PCLMUL |
- CPUID2_DTES64 | CPUID2_DS_CPL |
- CPUID2_SSSE3 | CPUID2_CID |
- CPUID2_SDBG | CPUID2_FMA |
- CPUID2_CX16 | CPUID2_xTPR |
- CPUID2_SSE41 | CPUID2_SSE42 |
- CPUID2_MOVBE | CPUID2_POPCNT |
- CPUID2_AES | CPUID2_XSAVE |
- CPUID2_OSXSAVE | CPUID2_F16C |
+ CPUID2_SSE3 |
+ CPUID2_PCLMUL |
+ CPUID2_DTES64 |
+ /* CPUID2_MONITOR excluded */
+ CPUID2_DS_CPL |
+ /* CPUID2_VMX excluded */
+ /* CPUID2_SMX excluded */
+ /* CPUID2_EST excluded */
+ /* CPUID2_TM2 excluded */
+ CPUID2_SSSE3 |
+ CPUID2_CID |
+ CPUID2_SDBG |
+ CPUID2_FMA |
+ CPUID2_CX16 |
+ CPUID2_xTPR |
+ /* CPUID2_PDCM excluded */
+ /* CPUID2_PCID excluded, but re-included in VMX */
+ /* CPUID2_DCA excluded */
+ CPUID2_SSE41 |
+ CPUID2_SSE42 |
+ /* CPUID2_X2APIC excluded */
+ CPUID2_MOVBE |
+ CPUID2_POPCNT |
+ /* CPUID2_DEADLINE excluded */
+ CPUID2_AES |
+ CPUID2_XSAVE |
+ CPUID2_OSXSAVE |
+ /* CPUID2_AVX excluded */
+ CPUID2_F16C |
CPUID2_RDRAND,
+ /* CPUID2_RAZ excluded */
.edx =
- /* Excluded: MCE, MTRR, MCA, DS, ACPI, TM. */
- CPUID_FPU | CPUID_VME |
- CPUID_DE | CPUID_PSE |
- CPUID_TSC | CPUID_MSR |
- CPUID_PAE | CPUID_CX8 |
- CPUID_APIC | CPUID_B10 |
- CPUID_SEP | CPUID_PGE |
- CPUID_CMOV | CPUID_PAT |
- CPUID_PSE36 | CPUID_PN |
- CPUID_CFLUSH | CPUID_B20 |
- CPUID_MMX | CPUID_FXSR |
- CPUID_SSE | CPUID_SSE2 |
- CPUID_SS | CPUID_HTT |
- CPUID_IA64 | CPUID_SBF
+ CPUID_FPU |
+ CPUID_VME |
+ CPUID_DE |
+ CPUID_PSE |
+ CPUID_TSC |
+ CPUID_MSR |
+ CPUID_PAE |
+ /* CPUID_MCE excluded */
+ CPUID_CX8 |
+ CPUID_APIC |
+ CPUID_B10 |
+ CPUID_SEP |
+ /* CPUID_MTRR excluded */
+ CPUID_PGE |
+ /* CPUID_MCA excluded */
+ CPUID_CMOV |
+ CPUID_PAT |
+ CPUID_PSE36 |
+ CPUID_PN |
+ CPUID_CFLUSH |
+ CPUID_B20 |
+ /* CPUID_DS excluded */
+ /* CPUID_ACPI excluded */
+ CPUID_MMX |
+ CPUID_FXSR |
+ CPUID_SSE |
+ CPUID_SSE2 |
+ CPUID_SS |
+ CPUID_HTT |
+ /* CPUID_TM excluded */
+ CPUID_IA64 |
+ CPUID_SBF
};
const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = {
.eax = ~0,
.ebx =
- /* Excluded: TSC_ADJUST, AVX2, INVPCID, QM, AVX512*, PT, SHA. */
CPUID_SEF_FSGSBASE |
- CPUID_SEF_SGX | CPUID_SEF_BMI1 |
- CPUID_SEF_HLE | CPUID_SEF_FDPEXONLY |
- CPUID_SEF_SMEP | CPUID_SEF_BMI2 |
- CPUID_SEF_ERMS | CPUID_SEF_RTM |
- CPUID_SEF_FPUCSDS | CPUID_SEF_PQE |
- CPUID_SEF_RDSEED | CPUID_SEF_ADX |
- CPUID_SEF_SMAP | CPUID_SEF_CLFLUSHOPT |
+ /* CPUID_SEF_TSC_ADJUST excluded */
+ CPUID_SEF_SGX |
+ CPUID_SEF_BMI1 |
+ CPUID_SEF_HLE |
+ /* CPUID_SEF_AVX2 excluded */
+ CPUID_SEF_FDPEXONLY |
+ CPUID_SEF_SMEP |
+ CPUID_SEF_BMI2 |
+ CPUID_SEF_ERMS |
+ /* CPUID_SEF_INVPCID excluded, but re-included in VMX */
+ CPUID_SEF_RTM |
+ /* CPUID_SEF_QM excluded */
+ CPUID_SEF_FPUCSDS |
+ /* CPUID_SEF_MPX excluded */
+ CPUID_SEF_PQE |
+ /* CPUID_SEF_AVX512F excluded */
+ /* CPUID_SEF_AVX512DQ excluded */
+ CPUID_SEF_RDSEED |
+ CPUID_SEF_ADX |
+ CPUID_SEF_SMAP |
+ /* CPUID_SEF_AVX512_IFMA excluded */
+ CPUID_SEF_CLFLUSHOPT |
CPUID_SEF_CLWB,
+ /* CPUID_SEF_PT excluded */
+ /* CPUID_SEF_AVX512PF excluded */
+ /* CPUID_SEF_AVX512ER excluded */
+ /* CPUID_SEF_AVX512CD excluded */
+ /* CPUID_SEF_SHA excluded */
+ /* CPUID_SEF_AVX512BW excluded */
+ /* CPUID_SEF_AVX512VL excluded */
.ecx =
- /* Excluded: AVX512*, MAWAU, RDPID. */
- CPUID_SEF_PREFETCHWT1 | CPUID_SEF_UMIP |
- CPUID_SEF_PKU | CPUID_SEF_OSPKE |
- CPUID_SEF_WAITPKG | CPUID_SEF_GFNI |
- CPUID_SEF_VAES | CPUID_SEF_VPCLMULQDQ |
- CPUID_SEF_CLDEMOTE | CPUID_SEF_MOVDIRI |
- CPUID_SEF_MOVDIR64B | CPUID_SEF_SGXLC,
+ CPUID_SEF_PREFETCHWT1 |
+ /* CPUID_SEF_AVX512_VBMI excluded */
+ CPUID_SEF_UMIP |
+ CPUID_SEF_PKU |
+ CPUID_SEF_OSPKE |
+ CPUID_SEF_WAITPKG |
+ /* CPUID_SEF_AVX512_VBMI2 excluded */
+ /* CPUID_SEF_CET_SS excluded */
+ CPUID_SEF_GFNI |
+ CPUID_SEF_VAES |
+ CPUID_SEF_VPCLMULQDQ |
+ /* CPUID_SEF_AVX512_VNNI excluded */
+ /* CPUID_SEF_AVX512_BITALG excluded */
+ /* CPUID_SEF_AVX512_VPOPCNTDQ excluded */
+ /* CPUID_SEF_MAWAU excluded */
+ /* CPUID_SEF_RDPID excluded */
+ CPUID_SEF_CLDEMOTE |
+ CPUID_SEF_MOVDIRI |
+ CPUID_SEF_MOVDIR64B |
+ CPUID_SEF_SGXLC,
+ /* CPUID_SEF_PKS excluded */
.edx =
- /* Excluded: all except MD_CLEAR and ARCH_CAP. */
- CPUID_SEF_MD_CLEAR | CPUID_SEF_ARCH_CAP
+ /* CPUID_SEF_AVX512_4VNNIW excluded */
+ /* CPUID_SEF_AVX512_4FMAPS excluded */
+ /* CPUID_SEF_FSREP_MOV excluded */
+ /* CPUID_SEF_AVX512_VP2INTERSECT excluded */
+ /* CPUID_SEF_SRBDS_CTRL excluded */
+ CPUID_SEF_MD_CLEAR |
+ /* CPUID_SEF_TSX_FORCE_ABORT excluded */
+ /* CPUID_SEF_SERIALIZE excluded */
+ /* CPUID_SEF_HYBRID excluded */
+ /* CPUID_SEF_TSXLDTRK excluded */
+ /* CPUID_SEF_CET_IBT excluded */
+ /* CPUID_SEF_IBRS excluded */
+ /* CPUID_SEF_STIBP excluded */
+ /* CPUID_SEF_L1D_FLUSH excluded */
+ CPUID_SEF_ARCH_CAP
+ /* CPUID_SEF_CORE_CAP excluded */
+ /* CPUID_SEF_SSBD excluded */
};
const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001 = {
.eax = ~0,
.ebx = ~0,
.ecx =
- /* Excluded: SVM, EAPIC, OSVW, MWAITX. */
- CPUID_LAHF | CPUID_CMPLEGACY |
- CPUID_ALTMOVCR0 | CPUID_LZCNT |
- CPUID_SSE4A | CPUID_MISALIGNSSE |
- CPUID_3DNOWPF | CPUID_IBS |
- CPUID_XOP | CPUID_SKINIT |
- CPUID_WDT | CPUID_LWP |
- CPUID_FMA4 | CPUID_TCE |
- CPUID_NODEID | CPUID_TBM |
- CPUID_TOPOEXT | CPUID_PCEC |
- CPUID_PCENB | CPUID_SPM |
- CPUID_DBE | CPUID_PTSC |
+ CPUID_LAHF |
+ CPUID_CMPLEGACY |
+ /* CPUID_SVM excluded */
+ /* CPUID_EAPIC excluded */
+ CPUID_ALTMOVCR0 |
+ CPUID_LZCNT |
+ CPUID_SSE4A |
+ CPUID_MISALIGNSSE |
+ CPUID_3DNOWPF |
+ /* CPUID_OSVW excluded */
+ CPUID_IBS |
+ CPUID_XOP |
+ CPUID_SKINIT |
+ CPUID_WDT |
+ CPUID_LWP |
+ CPUID_FMA4 |
+ CPUID_TCE |
+ CPUID_NODEID |
+ CPUID_TBM |
+ CPUID_TOPOEXT |
+ CPUID_PCEC |
+ CPUID_PCENB |
+ CPUID_SPM |
+ CPUID_DBE |
+ CPUID_PTSC |
CPUID_L2IPERFC,
+ /* CPUID_MWAITX excluded */
.edx =
- /* Excluded: RDTSCP. */
- CPUID_SYSCALL | CPUID_MPC |
- CPUID_XD | CPUID_MMXX |
- CPUID_MMX | CPUID_FXSR |
- CPUID_FFXSR | CPUID_P1GB |
- CPUID_EM64T | CPUID_3DNOW2 |
+ CPUID_SYSCALL |
+ CPUID_MPC |
+ CPUID_XD |
+ CPUID_MMXX |
+ CPUID_MMX |
+ CPUID_FXSR |
+ CPUID_FFXSR |
+ CPUID_P1GB |
+ /* CPUID_RDTSCP excluded */
+ CPUID_EM64T |
+ CPUID_3DNOW2 |
CPUID_3DNOW
};
Index: src/sys/dev/nvmm/x86/nvmm_x86_svm.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.7 src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.8
--- src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.7 Wed Aug 5 15:18:24 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_svm.c Tue Aug 18 09:29:52 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.7 2020/08/05 15:18:24 martin Exp $ */
+/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.8 2020/08/18 09:29:52 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.7 2020/08/05 15:18:24 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.8 2020/08/18 09:29:52 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -220,11 +220,16 @@ int svm_vmrun(paddr_t, uint64_t *);
#define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D
#define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E
#define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F
+#define VMCB_EXITCODE_INVLPGB 0x00A0
+#define VMCB_EXITCODE_INVLPGB_ILLEGAL 0x00A1
+#define VMCB_EXITCODE_INVPCID 0x00A2
#define VMCB_EXITCODE_MCOMMIT 0x00A3
+#define VMCB_EXITCODE_TLBSYNC 0x00A4
#define VMCB_EXITCODE_NPF 0x0400
#define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401
#define VMCB_EXITCODE_AVIC_NOACCEL 0x0402
#define VMCB_EXITCODE_VMGEXIT 0x0403
+#define VMCB_EXITCODE_BUSY -2ULL
#define VMCB_EXITCODE_INVALID -1ULL
/* -------------------------------------------------------------------------- */
@@ -295,7 +300,11 @@ struct vmcb_ctrl {
#define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x)
uint32_t intercept_misc3;
+#define VMCB_CTRL_INTERCEPT_INVLPGB_ALL __BIT(0)
+#define VMCB_CTRL_INTERCEPT_INVLPGB_ILL __BIT(1)
+#define VMCB_CTRL_INTERCEPT_PCID __BIT(2)
#define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3)
+#define VMCB_CTRL_INTERCEPT_TLBSYNC __BIT(4)
uint8_t rsvd1[36];
uint16_t pause_filt_thresh;
@@ -323,6 +332,7 @@ struct vmcb_ctrl {
uint64_t intr;
#define VMCB_CTRL_INTR_SHADOW __BIT(0)
+#define VMCB_CTRL_INTR_MASK __BIT(1)
uint64_t exitcode;
uint64_t exitinfo1;
@@ -387,7 +397,7 @@ struct vmcb_ctrl {
#define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0)
uint64_t rsvd4;
- uint64_t vmcb_ptr;
+ uint64_t vmsa_ptr;
uint8_t pad[752];
} __packed;
@@ -1443,6 +1453,11 @@ svm_vcpu_run(struct nvmm_machine *mach,
case VMCB_EXITCODE_CLGI:
case VMCB_EXITCODE_SKINIT:
case VMCB_EXITCODE_RDTSCP:
+ case VMCB_EXITCODE_RDPRU:
+ case VMCB_EXITCODE_INVLPGB:
+ case VMCB_EXITCODE_INVPCID:
+ case VMCB_EXITCODE_MCOMMIT:
+ case VMCB_EXITCODE_TLBSYNC:
svm_inject_ud(vcpu);
exit->reason = NVMM_VCPU_EXIT_NONE;
break;
@@ -2035,7 +2050,17 @@ svm_vcpu_init(struct nvmm_machine *mach,
VMCB_CTRL_INTERCEPT_RDTSCP |
VMCB_CTRL_INTERCEPT_MONITOR |
VMCB_CTRL_INTERCEPT_MWAIT |
- VMCB_CTRL_INTERCEPT_XSETBV;
+ VMCB_CTRL_INTERCEPT_XSETBV |
+ VMCB_CTRL_INTERCEPT_RDPRU;
+
+ /*
+ * Intercept everything.
+ */
+ vmcb->ctrl.intercept_misc3 =
+ VMCB_CTRL_INTERCEPT_INVLPGB_ALL |
+ VMCB_CTRL_INTERCEPT_PCID |
+ VMCB_CTRL_INTERCEPT_MCOMMIT |
+ VMCB_CTRL_INTERCEPT_TLBSYNC;
/* Intercept all I/O accesses. */
memset(cpudata->iobm, 0xFF, IOBM_SIZE);
Index: src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.9 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.10
--- src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.9 Wed Aug 5 15:18:24 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_vmx.c Tue Aug 18 09:29:52 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.9 2020/08/05 15:18:24 martin Exp $ */
+/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.10 2020/08/18 09:29:52 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.9 2020/08/05 15:18:24 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.10 2020/08/18 09:29:52 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -211,11 +211,16 @@ vmx_vmclear(paddr_t *pa)
#define MSR_IA32_VMX_CR4_FIXED1 0x0489
#define MSR_IA32_VMX_EPT_VPID_CAP 0x048C
+#define IA32_VMX_EPT_VPID_XO __BIT(0)
#define IA32_VMX_EPT_VPID_WALKLENGTH_4 __BIT(6)
#define IA32_VMX_EPT_VPID_UC __BIT(8)
#define IA32_VMX_EPT_VPID_WB __BIT(14)
+#define IA32_VMX_EPT_VPID_2MB __BIT(16)
+#define IA32_VMX_EPT_VPID_1GB __BIT(17)
#define IA32_VMX_EPT_VPID_INVEPT __BIT(20)
#define IA32_VMX_EPT_VPID_FLAGS_AD __BIT(21)
+#define IA32_VMX_EPT_VPID_ADVANCED_VMEXIT_INFO __BIT(22)
+#define IA32_VMX_EPT_VPID_SHSTK __BIT(23)
#define IA32_VMX_EPT_VPID_INVEPT_CONTEXT __BIT(25)
#define IA32_VMX_EPT_VPID_INVEPT_ALL __BIT(26)
#define IA32_VMX_EPT_VPID_INVVPID __BIT(32)
@@ -269,6 +274,7 @@ vmx_vmclear(paddr_t *pa)
#define EPTP_TYPE_WB 6
#define EPTP_WALKLEN __BITS(5,3)
#define EPTP_FLAGS_AD __BIT(6)
+#define EPTP_SSS __BIT(7)
#define EPTP_PHYSADDR __BITS(63,12)
#define VMCS_EOI_EXIT0 0x0000201C
#define VMCS_EOI_EXIT1 0x0000201E
@@ -282,6 +288,7 @@ vmx_vmclear(paddr_t *pa)
#define VMCS_ENCLS_EXIT_BITMAP 0x0000202E
#define VMCS_SUBPAGE_PERM_TABLE_PTR 0x00002030
#define VMCS_TSC_MULTIPLIER 0x00002032
+#define VMCS_ENCLV_EXIT_BITMAP 0x00002036
/* 64-bit read-only fields */
#define VMCS_GUEST_PHYSICAL_ADDRESS 0x00002400
/* 64-bit guest-state fields */
@@ -295,10 +302,13 @@ vmx_vmclear(paddr_t *pa)
#define VMCS_GUEST_PDPTE2 0x0000280E
#define VMCS_GUEST_PDPTE3 0x00002810
#define VMCS_GUEST_BNDCFGS 0x00002812
+#define VMCS_GUEST_RTIT_CTL 0x00002814
+#define VMCS_GUEST_PKRS 0x00002818
/* 64-bit host-state fields */
#define VMCS_HOST_IA32_PAT 0x00002C00
#define VMCS_HOST_IA32_EFER 0x00002C02
#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x00002C04
+#define VMCS_HOST_IA32_PKRS 0x00002C06
/* 32-bit control fields */
#define VMCS_PINBASED_CTLS 0x00004000
#define PIN_CTLS_INT_EXITING __BIT(0)
@@ -344,6 +354,9 @@ vmx_vmclear(paddr_t *pa)
#define EXIT_CTLS_SAVE_PREEMPT_TIMER __BIT(22)
#define EXIT_CTLS_CLEAR_BNDCFGS __BIT(23)
#define EXIT_CTLS_CONCEAL_PT __BIT(24)
+#define EXIT_CTLS_CLEAR_RTIT_CTL __BIT(25)
+#define EXIT_CTLS_LOAD_CET __BIT(28)
+#define EXIT_CTLS_LOAD_PKRS __BIT(29)
#define VMCS_EXIT_MSR_STORE_COUNT 0x0000400E
#define VMCS_EXIT_MSR_LOAD_COUNT 0x00004010
#define VMCS_ENTRY_CTLS 0x00004012
@@ -356,6 +369,9 @@ vmx_vmclear(paddr_t *pa)
#define ENTRY_CTLS_LOAD_EFER __BIT(15)
#define ENTRY_CTLS_LOAD_BNDCFGS __BIT(16)
#define ENTRY_CTLS_CONCEAL_PT __BIT(17)
+#define ENTRY_CTLS_LOAD_RTIT_CTL __BIT(18)
+#define ENTRY_CTLS_LOAD_CET __BIT(20)
+#define ENTRY_CTLS_LOAD_PKRS __BIT(22)
#define VMCS_ENTRY_MSR_LOAD_COUNT 0x00004014
#define VMCS_ENTRY_INTR_INFO 0x00004016
#define INTR_INFO_VECTOR __BITS(7,0)
@@ -396,7 +412,9 @@ vmx_vmclear(paddr_t *pa)
#define PROC_CTLS2_XSAVES_ENABLE __BIT(20)
#define PROC_CTLS2_MODE_BASED_EXEC_EPT __BIT(22)
#define PROC_CTLS2_SUBPAGE_PERMISSIONS __BIT(23)
+#define PROC_CTLS2_PT_USES_GPA __BIT(24)
#define PROC_CTLS2_USE_TSC_SCALING __BIT(25)
+#define PROC_CTLS2_WAIT_PAUSE_ENABLE __BIT(26)
#define PROC_CTLS2_ENCLV_EXITING __BIT(28)
#define VMCS_PLE_GAP 0x00004020
#define VMCS_PLE_WINDOW 0x00004022
@@ -477,6 +495,9 @@ vmx_vmclear(paddr_t *pa)
#define VMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822
#define VMCS_GUEST_IA32_SYSENTER_ESP 0x00006824
#define VMCS_GUEST_IA32_SYSENTER_EIP 0x00006826
+#define VMCS_GUEST_IA32_S_CET 0x00006828
+#define VMCS_GUEST_SSP 0x0000682A
+#define VMCS_GUEST_IA32_INTR_SSP_TABLE 0x0000682C
/* Natural-Width host-state fields */
#define VMCS_HOST_CR0 0x00006C00
#define VMCS_HOST_CR3 0x00006C02
@@ -490,6 +511,9 @@ vmx_vmclear(paddr_t *pa)
#define VMCS_HOST_IA32_SYSENTER_EIP 0x00006C12
#define VMCS_HOST_RSP 0x00006C14
#define VMCS_HOST_RIP 0x00006C16
+#define VMCS_HOST_IA32_S_CET 0x00006C18
+#define VMCS_HOST_SSP 0x00006C1A
+#define VMCS_HOST_IA32_INTR_SSP_TABLE 0x00006C1C
/* VMX basic exit reasons. */
#define VMCS_EXITCODE_EXC_NMI 0
@@ -554,6 +578,9 @@ vmx_vmclear(paddr_t *pa)
#define VMCS_EXITCODE_PAGE_LOG_FULL 62
#define VMCS_EXITCODE_XSAVES 63
#define VMCS_EXITCODE_XRSTORS 64
+#define VMCS_EXITCODE_SPP 66
+#define VMCS_EXITCODE_UMWAIT 67
+#define VMCS_EXITCODE_TPAUSE 68
/* -------------------------------------------------------------------------- */
