Module Name: src
Committed By: maxv
Date: Fri Sep 4 17:05:09 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add a few more CPUID flags.
To generate a diff of this commit:
cvs rdiff -u -r1.171 -r1.172 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.171 src/sys/arch/x86/include/specialreg.h:1.172
--- src/sys/arch/x86/include/specialreg.h:1.171 Wed Aug 5 15:40:46 2020
+++ src/sys/arch/x86/include/specialreg.h Fri Sep 4 17:05:09 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.171 2020/08/05 15:40:46 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.172 2020/09/04 17:05:09 maxv Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -759,6 +759,11 @@
#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
+/* %ecx */
+#define CPUID_CAPEX_PerfTscSize __BITS(17,16)
+#define CPUID_CAPEX_ApicIdSize __BITS(15,12)
+#define CPUID_CAPEX_NC __BITS(7,0)
+
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
"\5RDPRU" "\7B6" \
@@ -767,6 +772,9 @@
"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
+/* AMD Fn8000_000a %eax (SVM Revision) */
+#define CPUID_AMD_SVM_REV __BITS(7,0)
+
/* AMD Fn8000_000a %edx features (SVM features) */
#define CPUID_AMD_SVM_NP 0x00000001
#define CPUID_AMD_SVM_LbrVirt 0x00000002
