Module Name: src
Committed By: maxv
Date: Sat Sep 5 07:45:45 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: identcpu.c
src/sys/crypto/aes/arch/x86: aes_ni.c
src/sys/dev/nvmm/x86: nvmm_x86.c
src/sys/external/bsd/drm2/drm: drm_cache.c
src/sys/external/bsd/drm2/include/asm: cpufeature.h
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
x86: fix several CPUID flags
- Rename: CPUID_PN -> CPUID_PSN
CPUID_CFLUSH -> CPUID_CLFSH
CPUID_SBF -> CPUID_PBE
CPUID_LZCNT -> CPUID_ABM
CPUID_P1GB -> CPUID_PAGE1GB
CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
CPUID2_CID -> CPUID2_CNXTID
CPUID2_xTPR -> CPUID2_XTPR
CPUID2_AES -> CPUID2_AESNI
To match the x86 specification and the other OSes.
- Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
To generate a diff of this commit:
cvs rdiff -u -r1.172 -r1.173 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.116 -r1.117 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.4 -r1.5 src/sys/crypto/aes/arch/x86/aes_ni.c
cvs rdiff -u -r1.17 -r1.18 src/sys/dev/nvmm/x86/nvmm_x86.c
cvs rdiff -u -r1.13 -r1.14 src/sys/external/bsd/drm2/drm/drm_cache.c
cvs rdiff -u -r1.4 -r1.5 src/sys/external/bsd/drm2/include/asm/cpufeature.h
cvs rdiff -u -r1.113 -r1.114 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.172 src/sys/arch/x86/include/specialreg.h:1.173
--- src/sys/arch/x86/include/specialreg.h:1.172 Fri Sep 4 17:05:09 2020
+++ src/sys/arch/x86/include/specialreg.h Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.172 2020/09/04 17:05:09 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.173 2020/09/05 07:45:44 maxv Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -185,7 +185,6 @@
#define CPUID_MCE 0x00000080 /* has machine check exception */
#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
#define CPUID_APIC 0x00000200 /* has enabled APIC */
-#define CPUID_B10 0x00000400 /* reserved, MTRR */
#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
#define CPUID_MTRR 0x00001000 /* has memory type range register */
#define CPUID_PGE 0x00002000 /* has page global extension */
@@ -193,9 +192,8 @@
#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
#define CPUID_PAT 0x00010000 /* Page Attribute Table */
#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
-#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */
-#define CPUID_B20 0x00100000 /* reserved */
+#define CPUID_PSN 0x00040000 /* processor serial number */
+#define CPUID_CLFSH 0x00080000 /* CLFLUSH insn supported */
#define CPUID_DS 0x00200000 /* Debug Store */
#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
#define CPUID_MMX 0x00800000 /* MMX supported */
@@ -205,8 +203,7 @@
#define CPUID_SS 0x08000000 /* self-snoop */
#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
-#define CPUID_IA64 0x40000000 /* IA-64 architecture */
-#define CPUID_SBF 0x80000000 /* signal break on FERR */
+#define CPUID_PBE 0x80000000 /* Pending Break Enable */
#define CPUID_FLAGS1 "\20" \
"\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
@@ -230,7 +227,7 @@
*/
#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
-#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
+#define CPUID2_PCLMULQDQ 0x00000002 /* PCLMULQDQ instructions */
#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
@@ -239,11 +236,11 @@
#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
-#define CPUID2_CID 0x00000400 /* Context ID */
+#define CPUID2_CNXTID 0x00000400 /* Context ID */
#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
-#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
+#define CPUID2_XTPR 0x00004000 /* Task Priority Messages disabled? */
#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
/* bit 16 unused 0x00010000 */
#define CPUID2_PCID 0x00020000 /* Process Context ID */
@@ -254,7 +251,7 @@
#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
-#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_AESNI 0x02000000 /* AES instructions */
#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
#define CPUID2_AVX 0x10000000 /* AVX instructions */
@@ -625,7 +622,7 @@
/* Intel Fn80000001 extended features - %edx */
#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
-#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
+#define CPUID_PAGE1GB 0x04000000 /* 1GB Large Page Support */
#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
#define CPUID_EM64T 0x20000000 /* Intel EM64T */
@@ -635,7 +632,7 @@
/* Intel Fn80000001 extended features - %ecx */
#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
- /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */
+ /* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_ABM */
#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
#define CPUID_INTEL_FLAGS4 "\20" \
@@ -652,7 +649,7 @@
/* CPUID_MMX MMX supported */
/* CPUID_FXSR fast FP/MMX save/restore */
#define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */
-/* CPUID_P1GB 1GB Large Page Support */
+/* CPUID_PAGE1GB 1GB Large Page Support */
/* CPUID_RDTSCP Read TSC Pair Instruction */
/* CPUID_EM64T Long mode */
#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
@@ -671,7 +668,7 @@
#define CPUID_SVM 0x00000004 /* Secure Virtual Machine */
#define CPUID_EAPIC 0x00000008 /* Extended APIC space */
#define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */
-#define CPUID_LZCNT 0x00000020 /* LZCNT instruction */
+#define CPUID_ABM 0x00000020 /* LZCNT instruction */
#define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */
#define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */
#define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.116 src/sys/arch/x86/x86/identcpu.c:1.117
--- src/sys/arch/x86/x86/identcpu.c:1.116 Sat Jul 25 22:49:20 2020
+++ src/sys/arch/x86/x86/identcpu.c Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.116 2020/07/25 22:49:20 riastradh Exp $ */
+/* $NetBSD: identcpu.c,v 1.117 2020/09/05 07:45:44 maxv Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.116 2020/07/25 22:49:20 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.117 2020/09/05 07:45:44 maxv Exp $");
#include "opt_xen.h"
@@ -924,7 +924,7 @@ cpu_probe(struct cpu_info *ci)
}
/* CLFLUSH line size is next 8 bits */
- if (ci->ci_feat_val[0] & CPUID_CFLUSH)
+ if (ci->ci_feat_val[0] & CPUID_CLFSH)
ci->ci_cflush_lsize
= __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3;
ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID);
@@ -1006,7 +1006,7 @@ cpu_probe(struct cpu_info *ci)
/* AES */
#ifdef __x86_64__ /* not yet implemented on i386 */
- if (cpu_feature[1] & CPUID2_AES)
+ if (cpu_feature[1] & CPUID2_AESNI)
aes_md_init(&aes_ni_impl);
else
#endif
Index: src/sys/crypto/aes/arch/x86/aes_ni.c
diff -u src/sys/crypto/aes/arch/x86/aes_ni.c:1.4 src/sys/crypto/aes/arch/x86/aes_ni.c:1.5
--- src/sys/crypto/aes/arch/x86/aes_ni.c:1.4 Sat Jul 25 22:29:06 2020
+++ src/sys/crypto/aes/arch/x86/aes_ni.c Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: aes_ni.c,v 1.4 2020/07/25 22:29:06 riastradh Exp $ */
+/* $NetBSD: aes_ni.c,v 1.5 2020/09/05 07:45:44 maxv Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: aes_ni.c,v 1.4 2020/07/25 22:29:06 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aes_ni.c,v 1.5 2020/09/05 07:45:44 maxv Exp $");
#ifdef _KERNEL
#include <sys/types.h>
@@ -283,7 +283,7 @@ aesni_probe(void)
/* Verify that the CPU supports AES-NI. */
#ifdef _KERNEL
- if ((cpu_feature[1] & CPUID2_AES) == 0)
+ if ((cpu_feature[1] & CPUID2_AESNI) == 0)
return -1;
#else
unsigned eax, ebx, ecx, edx;
Index: src/sys/dev/nvmm/x86/nvmm_x86.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86.c:1.17 src/sys/dev/nvmm/x86/nvmm_x86.c:1.18
--- src/sys/dev/nvmm/x86/nvmm_x86.c:1.17 Sat Sep 5 07:22:26 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86.c Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86.c,v 1.17 2020/09/05 07:22:26 maxv Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.18 2020/09/05 07:45:44 maxv Exp $ */
/*
* Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.17 2020/09/05 07:22:26 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.18 2020/09/05 07:45:44 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -233,7 +233,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
.ebx = ~0,
.ecx =
CPUID2_SSE3 |
- CPUID2_PCLMUL |
+ CPUID2_PCLMULQDQ |
/* CPUID2_DTES64 excluded */
/* CPUID2_MONITOR excluded */
/* CPUID2_DS_CPL excluded */
@@ -242,11 +242,11 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
/* CPUID2_EST excluded */
/* CPUID2_TM2 excluded */
CPUID2_SSSE3 |
- /* CPUID2_CID excluded */
+ /* CPUID2_CNXTID excluded */
/* CPUID2_SDBG excluded */
CPUID2_FMA |
CPUID2_CX16 |
- /* CPUID2_xTPR excluded */
+ /* CPUID2_XTPR excluded */
/* CPUID2_PDCM excluded */
/* CPUID2_PCID excluded, but re-included in VMX */
/* CPUID2_DCA excluded */
@@ -256,7 +256,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID2_MOVBE |
CPUID2_POPCNT |
/* CPUID2_DEADLINE excluded */
- CPUID2_AES |
+ CPUID2_AESNI |
CPUID2_XSAVE |
CPUID2_OSXSAVE |
/* CPUID2_AVX excluded */
@@ -281,8 +281,8 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID_CMOV |
CPUID_PAT |
CPUID_PSE36 |
- /* CPUID_PN excluded */
- CPUID_CFLUSH |
+ /* CPUID_PSN excluded */
+ CPUID_CLFSH |
/* CPUID_DS excluded */
/* CPUID_ACPI excluded */
CPUID_MMX |
@@ -292,7 +292,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID_SS |
CPUID_HTT |
/* CPUID_TM excluded */
- CPUID_SBF
+ CPUID_PBE
};
const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007 = {
@@ -380,7 +380,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
/* CPUID_SVM excluded */
/* CPUID_EAPIC excluded */
CPUID_ALTMOVCR0 |
- CPUID_LZCNT |
+ CPUID_ABM |
CPUID_SSE4A |
CPUID_MISALIGNSSE |
CPUID_3DNOWPF |
@@ -410,7 +410,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID_MMX |
CPUID_FXSR |
CPUID_FFXSR |
- CPUID_P1GB |
+ CPUID_PAGE1GB |
/* CPUID_RDTSCP excluded */
CPUID_EM64T |
CPUID_3DNOW2 |
Index: src/sys/external/bsd/drm2/drm/drm_cache.c
diff -u src/sys/external/bsd/drm2/drm/drm_cache.c:1.13 src/sys/external/bsd/drm2/drm/drm_cache.c:1.14
--- src/sys/external/bsd/drm2/drm/drm_cache.c:1.13 Wed Jan 23 19:02:49 2019
+++ src/sys/external/bsd/drm2/drm/drm_cache.c Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: drm_cache.c,v 1.13 2019/01/23 19:02:49 jmcneill Exp $ */
+/* $NetBSD: drm_cache.c,v 1.14 2020/09/05 07:45:44 maxv Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: drm_cache.c,v 1.13 2019/01/23 19:02:49 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: drm_cache.c,v 1.14 2020/09/05 07:45:44 maxv Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -123,7 +123,7 @@ drm_clflush_virt_range(const void *vaddr
static bool
drm_md_clflush_finegrained_p(void)
{
- return ISSET(cpu_info_primary.ci_feat_val[0], CPUID_CFLUSH);
+ return ISSET(cpu_info_primary.ci_feat_val[0], CPUID_CLFSH);
}
static void
Index: src/sys/external/bsd/drm2/include/asm/cpufeature.h
diff -u src/sys/external/bsd/drm2/include/asm/cpufeature.h:1.4 src/sys/external/bsd/drm2/include/asm/cpufeature.h:1.5
--- src/sys/external/bsd/drm2/include/asm/cpufeature.h:1.4 Mon Aug 27 13:44:15 2018
+++ src/sys/external/bsd/drm2/include/asm/cpufeature.h Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufeature.h,v 1.4 2018/08/27 13:44:15 riastradh Exp $ */
+/* $NetBSD: cpufeature.h,v 1.5 2020/09/05 07:45:44 maxv Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#if defined(__i386__) || defined(__x86_64__)
-#define cpu_has_clflush ((cpu_info_primary.ci_feat_val[0] & CPUID_CFLUSH) != 0)
+#define cpu_has_clflush ((cpu_info_primary.ci_feat_val[0] & CPUID_CLFSH) != 0)
#define cpu_has_pat ((cpu_info_primary.ci_feat_val[0] & CPUID_PAT) != 0)
static inline size_t
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.113 src/usr.sbin/cpuctl/arch/i386.c:1.114
--- src/usr.sbin/cpuctl/arch/i386.c:1.113 Mon Jun 1 08:33:40 2020
+++ src/usr.sbin/cpuctl/arch/i386.c Sat Sep 5 07:45:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.114 2020/09/05 07:45:44 maxv Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.114 2020/09/05 07:45:44 maxv Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -1627,7 +1627,7 @@ cpu_probe_base_features(struct cpu_info
* If the processor serial number misfeature is present and supported,
* extract it here.
*/
- if ((ci->ci_feat_val[0] & CPUID_PN) != 0) {
+ if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) {
ci->ci_cpu_serial[0] = ci->ci_signature;
x86_cpuid(3, descs);
ci->ci_cpu_serial[2] = descs[2];
@@ -2183,7 +2183,7 @@ identifycpu(int fd, const char *cpuname)
x86_print_cache_and_tlb_info(ci);
- if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) {
+ if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) {
aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n",
cpuname,
ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536,
