Module Name: src
Committed By: thorpej
Date: Sat Sep 5 16:29:08 UTC 2020
Modified Files:
src/sys/arch/alpha/alpha: genassym.cf interrupt.c locore.s
src/sys/arch/alpha/include: alpha_cpu.h intr.h
src/sys/arch/alpha/tc: tc_3000_300.c tc_3000_500.c
Log Message:
- Document all of the various interrupt levels in the Processor Stataus
register, and provide symbolic names for them as well.
- Use ALPHA_PSL_IPL_* values directly for IPL_*.
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/alpha/alpha/genassym.cf
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/alpha/alpha/interrupt.c
cvs rdiff -u -r1.130 -r1.131 src/sys/arch/alpha/alpha/locore.s
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/alpha/include/alpha_cpu.h
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/alpha/include/intr.h
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/alpha/tc/tc_3000_300.c
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/alpha/tc/tc_3000_500.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/alpha/alpha/genassym.cf
diff -u src/sys/arch/alpha/alpha/genassym.cf:1.23 src/sys/arch/alpha/alpha/genassym.cf:1.24
--- src/sys/arch/alpha/alpha/genassym.cf:1.23 Thu Sep 3 04:18:30 2020
+++ src/sys/arch/alpha/alpha/genassym.cf Sat Sep 5 16:29:07 2020
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.23 2020/09/03 04:18:30 thorpej Exp $
+# $NetBSD: genassym.cf,v 1.24 2020/09/05 16:29:07 thorpej Exp $
#
# Copyright (c) 1982, 1990, 1993
@@ -129,7 +129,7 @@ define FRAME_SIZE FRAME_SIZE
define ALPHA_PSL_USERMODE ALPHA_PSL_USERMODE
define ALPHA_PSL_IPL_MASK ALPHA_PSL_IPL_MASK
define ALPHA_PSL_IPL_0 ALPHA_PSL_IPL_0
-define ALPHA_PSL_IPL_SOFT ALPHA_PSL_IPL_SOFT
+define ALPHA_PSL_IPL_SOFT_LO ALPHA_PSL_IPL_SOFT_LO
define ALPHA_PSL_IPL_HIGH ALPHA_PSL_IPL_HIGH
# pte bits
Index: src/sys/arch/alpha/alpha/interrupt.c
diff -u src/sys/arch/alpha/alpha/interrupt.c:1.82 src/sys/arch/alpha/alpha/interrupt.c:1.83
--- src/sys/arch/alpha/alpha/interrupt.c:1.82 Sat Aug 29 15:29:30 2020
+++ src/sys/arch/alpha/alpha/interrupt.c Sat Sep 5 16:29:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.82 2020/08/29 15:29:30 thorpej Exp $ */
+/* $NetBSD: interrupt.c,v 1.83 2020/09/05 16:29:07 thorpej Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.82 2020/08/29 15:29:30 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.83 2020/09/05 16:29:07 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -463,7 +463,7 @@ spl0(void)
{
if (ssir) {
- (void) alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT);
+ (void) alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT_LO);
softintr_dispatch();
}
@@ -525,18 +525,3 @@ rlprintf(struct timeval *t, const char *
vprintf(fmt, ap);
va_end(ap);
}
-
-const static uint8_t ipl2psl_table[] = {
- [IPL_NONE] = ALPHA_PSL_IPL_0,
- [IPL_SOFTCLOCK] = ALPHA_PSL_IPL_SOFT,
- [IPL_VM] = ALPHA_PSL_IPL_IO,
- [IPL_SCHED] = ALPHA_PSL_IPL_CLOCK, /* also IPIs */
- [IPL_HIGH] = ALPHA_PSL_IPL_HIGH,
-};
-
-ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
-}
Index: src/sys/arch/alpha/alpha/locore.s
diff -u src/sys/arch/alpha/alpha/locore.s:1.130 src/sys/arch/alpha/alpha/locore.s:1.131
--- src/sys/arch/alpha/alpha/locore.s:1.130 Fri Sep 4 04:09:52 2020
+++ src/sys/arch/alpha/alpha/locore.s Sat Sep 5 16:29:07 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.130 2020/09/04 04:09:52 thorpej Exp $ */
+/* $NetBSD: locore.s,v 1.131 2020/09/05 16:29:07 thorpej Exp $ */
/*-
* Copyright (c) 1999, 2000, 2019 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
#include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.130 2020/09/04 04:09:52 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.131 2020/09/05 16:29:07 thorpej Exp $");
#include "assym.h"
@@ -283,7 +283,7 @@ LEAF(exception_return, 1) /* XXX shoul
/* NOTREACHED */
/* We've got a SIR */
-6: ldiq a0, ALPHA_PSL_IPL_SOFT
+6: ldiq a0, ALPHA_PSL_IPL_SOFT_LO
call_pal PAL_OSF1_swpipl
mov v0, s2 /* remember old IPL */
CALL(softintr_dispatch)
Index: src/sys/arch/alpha/include/alpha_cpu.h
diff -u src/sys/arch/alpha/include/alpha_cpu.h:1.50 src/sys/arch/alpha/include/alpha_cpu.h:1.51
--- src/sys/arch/alpha/include/alpha_cpu.h:1.50 Mon Feb 6 02:14:13 2012
+++ src/sys/arch/alpha/include/alpha_cpu.h Sat Sep 5 16:29:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: alpha_cpu.h,v 1.50 2012/02/06 02:14:13 matt Exp $ */
+/* $NetBSD: alpha_cpu.h,v 1.51 2020/09/05 16:29:08 thorpej Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -94,16 +94,34 @@ struct alpha_pcb {
* Processor Status Register [OSF/1 PALcode Specific]
*
* Includes user/kernel mode bit, interrupt priority levels, etc.
+ *
+ * Processor Status Summary
+ * ---------------------------------------------------------------------------
+ * PS<mode> PS<IPL> Mode Use
+ * ---------------------------------------------------------------------------
+ * 1 0 User User software
+ * 0 0 Kernel System software
+ * 0 1 Kernel System software
+ * 0 2 Kernel System software
+ * 0 3 Kernel Low priority device interrupts
+ * 0 4 Kernel High priority device interrupts
+ * 0 5 Kernel Clock, inter-proc interrupts
+ * 0 6 Kernel Real-time device interrupts
+ * 0 6 Kernel Correctable error reporting
+ * 0 7 Kernel Machine checks
*/
#define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
#define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
#define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
-#define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
-#define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
+#define ALPHA_PSL_IPL_SOFT_LO 0x0001 /* low pri soft ints disabled */
+#define ALPHA_PSL_IPL_SOFT_HI 0x0002 /* hi pri soft ints disabled */
+#define ALPHA_PSL_IPL_IO_LO 0x0003 /* low pri dev ints disabled */
+#define ALPHA_PSL_IPL_IO_HI 0x0004 /* hi pri dev ints disabled */
#define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
#define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
+#define ALPHA_PSL_IPL_MCHECK 0x0007 /* machine checks disabled */
#define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
Index: src/sys/arch/alpha/include/intr.h
diff -u src/sys/arch/alpha/include/intr.h:1.73 src/sys/arch/alpha/include/intr.h:1.74
--- src/sys/arch/alpha/include/intr.h:1.73 Sat Aug 29 20:07:00 2020
+++ src/sys/arch/alpha/include/intr.h Sat Sep 5 16:29:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.73 2020/08/29 20:07:00 thorpej Exp $ */
+/* $NetBSD: intr.h,v 1.74 2020/09/05 16:29:08 thorpej Exp $ */
/*-
* Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc.
@@ -92,33 +92,37 @@ struct scbvec {
};
/*
- * Alpha interrupts come in at one of 4 levels:
+ * Alpha interrupts come in at one of 3 levels:
*
- * software interrupt level
* i/o level 1
* i/o level 2
* clock level
*
* However, since we do not have any way to know which hardware
* level a particular i/o interrupt comes in on, we have to
- * whittle it down to 3.
+ * whittle it down to 2. In addition, there are 2 software interrupt
+ * levels available to system software.
*/
-#define IPL_NONE 0 /* no interrupt level */
-#define IPL_SOFTCLOCK 1 /* generic software interrupts */
-#define IPL_SOFTBIO 1 /* generic software interrupts */
-#define IPL_SOFTNET 1 /* generic software interrupts */
-#define IPL_SOFTSERIAL 1 /* generic software interrupts */
-#define IPL_VM 2 /* interrupts that can alloc mem */
-#define IPL_SCHED 3 /* clock interrupts */
-#define IPL_HIGH 4 /* all interrupts */
+#define IPL_NONE ALPHA_PSL_IPL_0
+#define IPL_SOFTCLOCK ALPHA_PSL_IPL_SOFT_LO
+#define IPL_SOFTBIO ALPHA_PSL_IPL_SOFT_LO
+#define IPL_SOFTNET ALPHA_PSL_IPL_SOFT_LO /* XXX HI */
+#define IPL_SOFTSERIAL ALPHA_PSL_IPL_SOFT_LO /* XXX HI */
+#define IPL_VM ALPHA_PSL_IPL_IO_HI
+#define IPL_SCHED ALPHA_PSL_IPL_CLOCK
+#define IPL_HIGH ALPHA_PSL_IPL_HIGH
typedef int ipl_t;
typedef struct {
uint8_t _psl;
} ipl_cookie_t;
-ipl_cookie_t makeiplcookie(ipl_t);
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+ return (ipl_cookie_t){._psl = (uint8_t)ipl};
+}
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
Index: src/sys/arch/alpha/tc/tc_3000_300.c
diff -u src/sys/arch/alpha/tc/tc_3000_300.c:1.34 src/sys/arch/alpha/tc/tc_3000_300.c:1.35
--- src/sys/arch/alpha/tc/tc_3000_300.c:1.34 Sun Nov 10 21:16:22 2019
+++ src/sys/arch/alpha/tc/tc_3000_300.c Sat Sep 5 16:29:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: tc_3000_300.c,v 1.34 2019/11/10 21:16:22 chs Exp $ */
+/* $NetBSD: tc_3000_300.c,v 1.35 2020/09/05 16:29:08 thorpej Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
@@ -29,7 +29,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.34 2019/11/10 21:16:22 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.35 2020/09/05 16:29:08 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -210,9 +210,9 @@ tc_3000_300_iointr(void *arg, unsigned l
if (vec != 0x800)
panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
s = splhigh();
- if (s != ALPHA_PSL_IPL_IO)
+ if (s != ALPHA_PSL_IPL_IO_HI)
panic("INVALID ASSUMPTION: IPL %d, not %d", s,
- ALPHA_PSL_IPL_IO);
+ ALPHA_PSL_IPL_IO_HI);
splx(s);
#endif
Index: src/sys/arch/alpha/tc/tc_3000_500.c
diff -u src/sys/arch/alpha/tc/tc_3000_500.c:1.33 src/sys/arch/alpha/tc/tc_3000_500.c:1.34
--- src/sys/arch/alpha/tc/tc_3000_500.c:1.33 Sun Nov 10 21:16:22 2019
+++ src/sys/arch/alpha/tc/tc_3000_500.c Sat Sep 5 16:29:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: tc_3000_500.c,v 1.33 2019/11/10 21:16:22 chs Exp $ */
+/* $NetBSD: tc_3000_500.c,v 1.34 2020/09/05 16:29:08 thorpej Exp $ */
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
@@ -29,7 +29,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.33 2019/11/10 21:16:22 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.34 2020/09/05 16:29:08 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -214,9 +214,9 @@ tc_3000_500_iointr(void *arg, unsigned l
if (vec != 0x800)
panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
s = splhigh();
- if (s != ALPHA_PSL_IPL_IO)
+ if (s != ALPHA_PSL_IPL_IO_HI)
panic("INVALID ASSUMPTION: IPL %d, not %d", s,
- ALPHA_PSL_IPL_IO);
+ ALPHA_PSL_IPL_IO_HI);
splx(s);
#endif
