Module Name: src
Committed By: ryo
Date: Tue Sep 15 09:28:21 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: genassym.cf locore.S locore_el2.S start.S
src/sys/arch/aarch64/include: armreg.h
Log Message:
fix typo
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/aarch64/genassym.cf
cvs rdiff -u -r1.72 -r1.73 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/locore_el2.S
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/start.S
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/genassym.cf
diff -u src/sys/arch/aarch64/aarch64/genassym.cf:1.30 src/sys/arch/aarch64/aarch64/genassym.cf:1.31
--- src/sys/arch/aarch64/aarch64/genassym.cf:1.30 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/genassym.cf Tue Sep 15 09:28:20 2020
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.30 2020/08/12 13:19:35 skrll Exp $
+# $NetBSD: genassym.cf,v 1.31 2020/09/15 09:28:20 ryo Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -365,7 +365,7 @@ define SCTLR_nTWE SCTLR_nTWE
define SCTLR_WXN SCTLR_WXN
define SCTLR_IESB SCTLR_IESB
define SCTLR_SPAN SCTLR_SPAN
-define SCTLR_EOE SCTLR_EOE
+define SCTLR_E0E SCTLR_E0E
define SCTLR_EE SCTLR_EE
define SCTLR_UCI SCTLR_UCI
define SCTLR_nTLSMD SCTLR_nTLSMD
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.72 src/sys/arch/aarch64/aarch64/locore.S:1.73
--- src/sys/arch/aarch64/aarch64/locore.S:1.72 Tue Sep 15 09:23:15 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Tue Sep 15 09:28:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.72 2020/09/15 09:23:15 ryo Exp $ */
+/* $NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -38,7 +38,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.72 2020/09/15 09:23:15 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -390,9 +390,9 @@ ENTRY_NP(cpu_mpstart)
1:
mrs x8, sctlr_el1
#ifdef __AARCH64EB__
- orr x8, x8, #(SCTLR_EE | SCTLR_EOE) /* set: Big Endian */
+ orr x8, x8, #(SCTLR_EE | SCTLR_E0E) /* set: Big Endian */
#else
- bic x8, x8, #(SCTLR_EE | SCTLR_EOE) /* clear: Little Endian */
+ bic x8, x8, #(SCTLR_EE | SCTLR_E0E) /* clear: Little Endian */
#endif
msr sctlr_el1, x8
isb
Index: src/sys/arch/aarch64/aarch64/locore_el2.S
diff -u src/sys/arch/aarch64/aarch64/locore_el2.S:1.6 src/sys/arch/aarch64/aarch64/locore_el2.S:1.7
--- src/sys/arch/aarch64/aarch64/locore_el2.S:1.6 Tue Sep 15 09:23:15 2020
+++ src/sys/arch/aarch64/aarch64/locore_el2.S Tue Sep 15 09:28:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.6 2020/09/15 09:23:15 ryo Exp $ */
+/* $NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.6 2020/09/15 09:23:15 ryo Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $")
/*
* For use in #include "locore_el2.S".
@@ -76,7 +76,7 @@ in_el2:
/* Set the bits that need to be 1 in SCTLR_EL1. */
ldr x2, .Lsctlr_res1
mrs x1, sctlr_el1
- and x1, x1, #(SCTLR_EE | SCTLR_EOE) /* keep SCTLR_EL1.{EE,E0E} */
+ and x1, x1, #(SCTLR_EE | SCTLR_E0E) /* keep SCTLR_EL1.{EE,E0E} */
orr x2, x2, x1
msr sctlr_el1, x2
Index: src/sys/arch/aarch64/aarch64/start.S
diff -u src/sys/arch/aarch64/aarch64/start.S:1.10 src/sys/arch/aarch64/aarch64/start.S:1.11
--- src/sys/arch/aarch64/aarch64/start.S:1.10 Tue Sep 15 09:23:15 2020
+++ src/sys/arch/aarch64/aarch64/start.S Tue Sep 15 09:28:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: start.S,v 1.10 2020/09/15 09:23:15 ryo Exp $ */
+/* $NetBSD: start.S,v 1.11 2020/09/15 09:28:20 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -33,7 +33,7 @@
#include <aarch64/asm.h>
#include "assym.h"
-RCSID("$NetBSD: start.S,v 1.10 2020/09/15 09:23:15 ryo Exp $")
+RCSID("$NetBSD: start.S,v 1.11 2020/09/15 09:28:20 ryo Exp $")
/*
* Padding at start of kernel image to make room for 64-byte header
@@ -63,9 +63,9 @@ start:
1:
mrs x8, sctlr_el1
#ifdef __AARCH64EB__
- orr x8, x8, #(SCTLR_EE | SCTLR_EOE) /* set: Big Endian */
+ orr x8, x8, #(SCTLR_EE | SCTLR_E0E) /* set: Big Endian */
#else
- bic x8, x8, #(SCTLR_EE | SCTLR_EOE) /* clear: Little Endian */
+ bic x8, x8, #(SCTLR_EE | SCTLR_E0E) /* clear: Little Endian */
#endif
msr sctlr_el1, x8
isb
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.52 src/sys/arch/aarch64/include/armreg.h:1.53
--- src/sys/arch/aarch64/include/armreg.h:1.52 Sun Aug 2 06:58:16 2020
+++ src/sys/arch/aarch64/include/armreg.h Tue Sep 15 09:28:21 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.52 2020/08/02 06:58:16 maxv Exp $ */
+/* $NetBSD: armreg.h,v 1.53 2020/09/15 09:28:21 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -826,7 +826,7 @@ AARCH64REG_WRITE_INLINE(sctlr_el1)
#define SCTLR_IESB __BIT(21)
#define SCTLR_EIS __BIT(22)
#define SCTLR_SPAN __BIT(23)
-#define SCTLR_EOE __BIT(24)
+#define SCTLR_E0E __BIT(24)
#define SCTLR_EE __BIT(25)
#define SCTLR_UCI __BIT(26)
#define SCTLR_EnDA __BIT(27)
