Module Name: src
Committed By: ryo
Date: Wed Sep 30 08:40:49 UTC 2020
Modified Files:
src/sys/arch/aarch64/include: armreg.h
Log Message:
add some fields of ID_AA64ISAR1_EL1 definition (ARMv8.6)
To generate a diff of this commit:
cvs rdiff -u -r1.53 -r1.54 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.53 src/sys/arch/aarch64/include/armreg.h:1.54
--- src/sys/arch/aarch64/include/armreg.h:1.53 Tue Sep 15 09:28:21 2020
+++ src/sys/arch/aarch64/include/armreg.h Wed Sep 30 08:40:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.53 2020/09/15 09:28:21 ryo Exp $ */
+/* $NetBSD: armreg.h,v 1.54 2020/09/30 08:40:49 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -307,6 +307,15 @@ AARCH64REG_READ_INLINE(id_aa64isar0_el1)
AARCH64REG_READ_INLINE(id_aa64isar1_el1)
+#define ID_AA64ISAR1_EL1_I8MM __BITS(55,52)
+#define ID_AA64ISAR1_EL1_I8MM_NONE 0
+#define ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_DGH __BITS(51,48)
+#define ID_AA64ISAR1_EL1_DGH_NONE 0
+#define ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
+#define ID_AA64ISAR1_EL1_BF16 __BITS(47,44)
+#define ID_AA64ISAR1_EL1_BF16_NONE 0
+#define ID_AA64ISAR1_EL1_BF16_BFDOT 1
#define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
#define ID_AA64ISAR1_EL1_SPECRES_NONE 0
#define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
