Module Name: src
Committed By: mrg
Date: Sat Feb 13 08:46:23 UTC 2010
Modified Files:
src/sys/arch/sparc64/include: ctlreg.h
Log Message:
add some defines for the sizes of TLBs in various CPUs.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/sparc64/include/ctlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/ctlreg.h
diff -u src/sys/arch/sparc64/include/ctlreg.h:1.49 src/sys/arch/sparc64/include/ctlreg.h:1.50
--- src/sys/arch/sparc64/include/ctlreg.h:1.49 Mon Feb 1 06:26:15 2010
+++ src/sys/arch/sparc64/include/ctlreg.h Sat Feb 13 08:46:23 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.49 2010/02/01 06:26:15 mrg Exp $ */
+/* $NetBSD: ctlreg.h,v 1.50 2010/02/13 08:46:23 mrg Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -365,6 +365,17 @@
#define DEMAP_ALL ((0x08)<<4) /* Demap all non-locked TLB entries [USIII] */
/*
+ * These define the sizes of the TLB in various CPUs.
+ * They're mostly not necessary except for diagnostic code.
+ */
+#define TLB_SIZE_SPITFIRE 64
+#define TLB_SIZE_CHEETAH_I16 16
+#define TLB_SIZE_CHEETAH_I128 128
+#define TLB_SIZE_CHEETAH_D16 16
+#define TLB_SIZE_CHEETAH_D512_0 512
+#define TLB_SIZE_CHEETAH_D512_1 512
+
+/*
* Interrupt registers. This really gets hairy.
*/
