Module Name: src
Committed By: skrll
Date: Sat Nov 21 19:55:49 UTC 2020
Modified Files:
src/sys/arch/arm/xscale: i80200_irq.S
Log Message:
Adjust egister usage so that r4 and r5 are preserved as cur{cpu,lwp}
respectively as required by the change to make ASTs operate per-LWP
rather than per-CPU. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS expects this.
XXX untested
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/xscale/i80200_irq.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xscale/i80200_irq.S
diff -u src/sys/arch/arm/xscale/i80200_irq.S:1.18 src/sys/arch/arm/xscale/i80200_irq.S:1.19
--- src/sys/arch/arm/xscale/i80200_irq.S:1.18 Thu Jul 12 10:46:42 2018
+++ src/sys/arch/arm/xscale/i80200_irq.S Sat Nov 21 19:55:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: i80200_irq.S,v 1.18 2018/07/12 10:46:42 maxv Exp $ */
+/* $NetBSD: i80200_irq.S,v 1.19 2020/11/21 19:55:49 skrll Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -63,7 +63,7 @@ ASENTRY_NP(irq_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC /* Push an interrupt frame */
- ENABLE_ALIGNMENT_FAULTS
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
/*
* Note that we have entered the IRQ handler. We are
@@ -78,7 +78,7 @@ ASENTRY_NP(irq_entry)
/*
* Get the interrupt status into a callee-save register.
*/
- mrc p13, 0, r5, c4, c0, 0
+ mrc p13, 0, r6, c4, c0, 0
/*
* XXX - any need to handle BMU interrupts?
@@ -91,7 +91,7 @@ ASENTRY_NP(irq_entry)
* interrupts disabled, and will return with interrupts
* disabled.
*/
- tst r5, #(INTSRC_II)
+ tst r6, #(INTSRC_II)
beq .Lextirq_return /* no external IRQ pending */
ldr r1, .Lintr_dispatch
mov r0, sp
