Module Name: src
Committed By: mrg
Date: Thu Dec 31 20:47:06 UTC 2020
Modified Files:
src/sys/arch/arm/dts: rk3328-rock64.dts
src/sys/arch/arm/rockchip: rk3328_cru.c rk_i2s.c
Log Message:
begin to make rock64 audio work.
- set status for "analog_sound" to enabled.
- add clocks for the i2s and spdif nodes.
- match "rockchip,rk3066-i2s", "rockchip,rk3188-i2s",
and "rockchip,rk3288-i2s".
this gets i2s and ausoc to attach, but no audio(4) yet.
to complete this probably also needs a codec driver (appears
to be rk3328 specific, unlike eg pinebookpro's es8316), and
support for "audio-graph-card" type sound cards.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/dts/rk3328-rock64.dts
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/rk3328_cru.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rk_i2s.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/dts/rk3328-rock64.dts
diff -u src/sys/arch/arm/dts/rk3328-rock64.dts:1.5 src/sys/arch/arm/dts/rk3328-rock64.dts:1.6
--- src/sys/arch/arm/dts/rk3328-rock64.dts:1.5 Thu Dec 12 00:46:31 2019
+++ src/sys/arch/arm/dts/rk3328-rock64.dts Thu Dec 31 20:47:05 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3328-rock64.dts,v 1.5 2019/12/12 00:46:31 jmcneill Exp $ */
+/* $NetBSD: rk3328-rock64.dts,v 1.6 2020/12/31 20:47:05 mrg Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <[email protected]>
@@ -32,3 +32,7 @@
&usbdrd3 {
status = "okay";
};
+
+&analog_sound {
+ status = "okay";
+};
Index: src/sys/arch/arm/rockchip/rk3328_cru.c
diff -u src/sys/arch/arm/rockchip/rk3328_cru.c:1.5 src/sys/arch/arm/rockchip/rk3328_cru.c:1.6
--- src/sys/arch/arm/rockchip/rk3328_cru.c:1.5 Wed May 15 01:24:43 2019
+++ src/sys/arch/arm/rockchip/rk3328_cru.c Thu Dec 31 20:47:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3328_cru.c,v 1.5 2019/05/15 01:24:43 mrg Exp $ */
+/* $NetBSD: rk3328_cru.c,v 1.6 2020/12/31 20:47:06 mrg Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <[email protected]>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.5 2019/05/15 01:24:43 mrg Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.6 2020/12/31 20:47:06 mrg Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -152,6 +152,12 @@ static const char * mux_2plls_parents[]
static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" };
static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" };
static const char * pclk_gmac_parents[] = { "aclk_gmac" };
+static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m" };
+static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "xin12m" };
+static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "xin12m" };
+static const char * mux_spdif_parents[] = { "clk_spdif_div", "clk_spdif_frac", "xin12m" };
+static const char * mux_i2s1out_parents[] = { "clk_i2s1", "xin12m" };
+static const char * mux_i2s2out_parents[] = { "clk_i2s2", "xin12m" };
static struct rk_cru_clk rk3328_cru_clks[] = {
RK_PLL(RK3328_PLL_APLL, "apll", pll_parents,
@@ -388,6 +394,74 @@ static struct rk_cru_clk rk3328_cru_clks
RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)),
RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, GRF_MAC_CON1, __BIT(10)),
RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, GRF_SOC_CON4, __BIT(14)),
+
+ /* I2S */
+ RK_COMPOSITE(0, "clk_i2s0_div", mux_2plls_parents,
+ CLKSEL_CON(6), /* muxdiv_reg */
+ __BIT(15), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(1), /* gate_reg */
+ __BIT(1), /* gate_mask */
+ 0),
+ RK_COMPOSITE(0, "clk_i2s1_div", mux_2plls_parents,
+ CLKSEL_CON(8), /* muxdiv_reg */
+ __BIT(15), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(1), /* gate_reg */
+ __BIT(4), /* gate_mask */
+ 0),
+ RK_COMPOSITE(0, "clk_i2s2_div", mux_2plls_parents,
+ CLKSEL_CON(10), /* muxdiv_reg */
+ __BIT(15), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(1), /* gate_reg */
+ __BIT(8), /* gate_mask */
+ 0),
+ RK_COMPOSITE(0, "clk_spdif_div", mux_2plls_parents,
+ CLKSEL_CON(12), /* muxdiv_reg */
+ __BIT(15), /* mux_mask */
+ __BITS(6,0), /* div_mask */
+ CLKGATE_CON(1), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ 0),
+ RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div",
+ CLKSEL_CON(7), /* frac_reg */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div",
+ CLKSEL_CON(9), /* frac_reg */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div",
+ CLKSEL_CON(11), /* frac_reg */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_COMPOSITE_FRAC(0, "clk_spdif_frac", "clk_spdif_div",
+ CLKSEL_CON(13), /* frac_reg */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(6), __BITS(9,8)),
+ RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(8), __BITS(9,8)),
+ RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(10), __BITS(9,8)),
+ RK_MUX(0, "clk_spdif_mux", mux_spdif_parents, CLKSEL_CON(10), __BITS(9,8)),
+ RK_GATE(RK3328_SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(1), 3),
+ RK_GATE(RK3328_SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(1), 6),
+ RK_GATE(RK3328_SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(1), 10),
+ RK_GATE(RK3328_SCLK_SPDIF, "clk_spdif", "clk_spdif_mux", CLKGATE_CON(1), 12),
+ RK_GATE(RK3328_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_bus_pre", CLKGATE_CON(15), 3),
+ RK_GATE(RK3328_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_bus_pre", CLKGATE_CON(15), 4),
+ RK_GATE(RK3328_HCLK_I2S2_2CH, "hclk_i2s2", "hclk_bus_pre", CLKGATE_CON(15), 5),
+ RK_GATE(RK3328_HCLK_SPDIF_8CH, "hclk_spdif", "hclk_bus_pre", CLKGATE_CON(15), 6),
+ RK_COMPOSITE(RK3328_SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_parents,
+ CLKSEL_CON(8), /* muxdiv_reg */
+ __BIT(12), /* mux_mask */
+ 0, /* div_mask */
+ CLKGATE_CON(7), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ RK_COMPOSITE_SET_RATE_PARENT),
+ RK_COMPOSITE(RK3328_SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_parents,
+ CLKSEL_CON(10), /* muxdiv_reg */
+ __BIT(12), /* mux_mask */
+ 0, /* div_mask */
+ CLKGATE_CON(11), /* gate_reg */
+ __BIT(12), /* gate_mask */
+ RK_COMPOSITE_SET_RATE_PARENT),
};
static int
Index: src/sys/arch/arm/rockchip/rk_i2s.c
diff -u src/sys/arch/arm/rockchip/rk_i2s.c:1.4 src/sys/arch/arm/rockchip/rk_i2s.c:1.5
--- src/sys/arch/arm/rockchip/rk_i2s.c:1.4 Thu Dec 31 06:44:11 2020
+++ src/sys/arch/arm/rockchip/rk_i2s.c Thu Dec 31 20:47:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: rk_i2s.c,v 1.4 2020/12/31 06:44:11 mrg Exp $ */
+/* $NetBSD: rk_i2s.c,v 1.5 2020/12/31 20:47:06 mrg Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <[email protected]>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_i2s.c,v 1.4 2020/12/31 06:44:11 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_i2s.c,v 1.5 2020/12/31 20:47:06 mrg Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -118,6 +118,9 @@ static const struct rk_i2s_config rk3399
};
static const struct of_compat_data compat_data[] = {
+ { "rockchip,rk3066-i2s", 0 },
+ { "rockchip,rk3188-i2s", 0 },
+ { "rockchip,rk3288-i2s", 0 },
{ "rockchip,rk3399-i2s", (uintptr_t)&rk3399_i2s_config },
{ NULL }
};
