Module Name: src
Committed By: rin
Date: Tue Mar 30 02:27:00 UTC 2021
Modified Files:
src/sys/arch/powerpc/ibm4xx: cpu.c
Log Message:
According to "PPC405GP Embedded Processor User’s Manual",
405GP has 16KB instruction cache, not 8KB.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/powerpc/ibm4xx/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/ibm4xx/cpu.c
diff -u src/sys/arch/powerpc/ibm4xx/cpu.c:1.36 src/sys/arch/powerpc/ibm4xx/cpu.c:1.37
--- src/sys/arch/powerpc/ibm4xx/cpu.c:1.36 Fri Mar 5 07:11:24 2021
+++ src/sys/arch/powerpc/ibm4xx/cpu.c Tue Mar 30 02:27:00 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $ */
+/* $NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.36 2021/03/05 07:11:24 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.37 2021/03/30 02:27:00 rin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -176,7 +176,7 @@ static const struct cputab models[] = {
.ci = {
.dcache_size = 8192,
.dcache_line_size = 32,
- .icache_size = 8192,
+ .icache_size = 16384,
.icache_line_size = 32,
}
}, {
