Module Name: src
Committed By: skrll
Date: Tue Apr 27 06:03:09 UTC 2021
Modified Files:
src/sys/arch/arm/include: lock.h
Log Message:
Fix the barrier confusion. From Riastradh - thanks!.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/include/lock.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/include/lock.h
diff -u src/sys/arch/arm/include/lock.h:1.37 src/sys/arch/arm/include/lock.h:1.38
--- src/sys/arch/arm/include/lock.h:1.37 Mon Apr 26 16:35:54 2021
+++ src/sys/arch/arm/include/lock.h Tue Apr 27 06:03:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: lock.h,v 1.37 2021/04/26 16:35:54 skrll Exp $ */
+/* $NetBSD: lock.h,v 1.38 2021/04/27 06:03:09 skrll Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -131,32 +131,34 @@ __swp(int __val, __cpu_simple_lock_t *__
}
#endif /* !_ARM_ARCH_6 */
+/* load/dmb implies load-acquire */
static __inline void
-__arm_membar_producer(void)
+__arm_load_dmb(void)
{
#if defined(_ARM_ARCH_7)
- __asm __volatile("dsb" ::: "memory");
+ __asm __volatile("dmb ish" ::: "memory");
#elif defined(_ARM_ARCH_6)
- __asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0) : "memory");
+ __asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
#endif
}
+/* dmb/store implies store-release */
static __inline void
-__arm_membar_consumer(void)
+__arm_dmb_store(void)
{
#if defined(_ARM_ARCH_7)
- __asm __volatile("dmb" ::: "memory");
+ __asm __volatile("dmb ish" ::: "memory");
#elif defined(_ARM_ARCH_6)
__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
#endif
}
+
static __inline void __unused
__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
{
*__alp = __SIMPLELOCK_UNLOCKED;
- __arm_membar_producer();
}
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
@@ -164,12 +166,11 @@ static __inline void __unused
__cpu_simple_lock(__cpu_simple_lock_t *__alp)
{
#if defined(_ARM_ARCH_6)
- __arm_membar_consumer();
do {
/* spin */
} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
|| __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
- __arm_membar_producer();
+ __arm_load_dmb();
#else
while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
continue;
@@ -184,13 +185,12 @@ static __inline int __unused
__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
{
#if defined(_ARM_ARCH_6)
- __arm_membar_consumer();
do {
if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
return 0;
}
} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
- __arm_membar_producer();
+ __arm_load_dmb();
return 1;
#else
return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
@@ -213,9 +213,8 @@ __cpu_simple_unlock(__cpu_simple_lock_t
:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
}
#else
- __arm_membar_consumer();
+ __arm_dmb_store();
*__alp = __SIMPLELOCK_UNLOCKED;
- __arm_membar_producer();
#endif
}
