Module Name: src
Committed By: jmcneill
Date: Sat Jun 19 13:40:00 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
src/sys/arch/aarch64/include: armreg.h
Log Message:
Do not try to initialize PMU if ID_AA64DFR0_EL1 reports a non-standard
PMU implementation.
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/aarch64/aarch64/cpu.c
cvs rdiff -u -r1.56 -r1.57 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.59 src/sys/arch/aarch64/aarch64/cpu.c:1.60
--- src/sys/arch/aarch64/aarch64/cpu.c:1.59 Tue Mar 9 16:44:27 2021
+++ src/sys/arch/aarch64/aarch64/cpu.c Sat Jun 19 13:40:00 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.59 2021/03/09 16:44:27 ryo Exp $ */
+/* $NetBSD: cpu.c,v 1.60 2021/06/19 13:40:00 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.59 2021/03/09 16:44:27 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.60 2021/06/19 13:40:00 jmcneill Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -486,6 +486,10 @@ cpu_init_counter(struct cpu_info *ci)
/* Performance Monitors Extension not implemented. */
return;
}
+ if (pmuver == ID_AA64DFR0_EL1_PMUVER_IMPL) {
+ /* Non-standard Performance Monitors are not supported. */
+ return;
+ }
reg_pmcr_el0_write(PMCR_E | PMCR_C);
reg_pmcntenset_el0_write(PMCNTEN_C);
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.56 src/sys/arch/aarch64/include/armreg.h:1.57
--- src/sys/arch/aarch64/include/armreg.h:1.56 Sat Jun 19 13:38:21 2021
+++ src/sys/arch/aarch64/include/armreg.h Sat Jun 19 13:40:00 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.56 2021/06/19 13:38:21 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.57 2021/06/19 13:40:00 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -248,6 +248,7 @@ AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
#define ID_AA64DFR0_EL1_PMUVER_NONE 0
#define ID_AA64DFR0_EL1_PMUVER_V3 1
#define ID_AA64DFR0_EL1_PMUVER_NOV3 2
+#define ID_AA64DFR0_EL1_PMUVER_IMPL 15
#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
#define ID_AA64DFR0_EL1_TRACEVER_NONE 0
#define ID_AA64DFR0_EL1_TRACEVER_IMPL 1
