Module Name:    src
Committed By:   mrg
Date:           Wed Jun 23 00:56:41 UTC 2021

Modified Files:
        src/sys/arch/arm/rockchip: rk_platform.c
        src/sys/dev/ic: ahcisata_core.c

Log Message:
make ahcisata(4) work on rk3399 (rockpro64)

on rk3399, a marvell 9230 ahci sata card consistently takes between
1213 and 1216 milliseconds, the ahci spec says this should complete
in 1000 or fewer.

add a "pcie-reset-ms" uint32 property that ahcisata defaults to 1000
if not set, and the rockchip platform code sets to 2000.

ok @jmcneill


To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/rockchip/rk_platform.c
cvs rdiff -u -r1.98 -r1.99 src/sys/dev/ic/ahcisata_core.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/rockchip/rk_platform.c
diff -u src/sys/arch/arm/rockchip/rk_platform.c:1.12 src/sys/arch/arm/rockchip/rk_platform.c:1.13
--- src/sys/arch/arm/rockchip/rk_platform.c:1.12	Sat Apr 24 23:36:28 2021
+++ src/sys/arch/arm/rockchip/rk_platform.c	Wed Jun 23 00:56:41 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: rk_platform.c,v 1.12 2021/04/24 23:36:28 thorpej Exp $ */
+/* $NetBSD: rk_platform.c,v 1.13 2021/06/23 00:56:41 mrg Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -31,7 +31,7 @@
 #include "opt_console.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_platform.c,v 1.12 2021/04/24 23:36:28 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_platform.c,v 1.13 2021/06/23 00:56:41 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -39,6 +39,8 @@ __KERNEL_RCSID(0, "$NetBSD: rk_platform.
 #include <sys/device.h>
 #include <sys/termios.h>
 
+#include <prop/proplib.h>
+
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 
@@ -70,6 +72,17 @@ rk_platform_init_attach_args(struct fdt_
 static void
 rk_platform_device_register(device_t self, void *aux)
 {
+	prop_dictionary_t dict = device_properties(self);
+
+	if (device_is_a(self, "ahcisata")) {
+		/*
+		 * Marvel 9230 AHCI SATA controllers take between 1213 and 1216
+		 * milliseconds to reset, exceeding the AHCI spec of 1000.
+		 */
+		if (!prop_dictionary_set_uint32(dict, "ahci-reset-ms", 2000))
+			printf("%s: Failed to set \"ahci-reset-ms\" property"
+			       " on ahcisata\n", __func__);
+	}
 }
 
 static void

Index: src/sys/dev/ic/ahcisata_core.c
diff -u src/sys/dev/ic/ahcisata_core.c:1.98 src/sys/dev/ic/ahcisata_core.c:1.99
--- src/sys/dev/ic/ahcisata_core.c:1.98	Sat Apr 24 23:36:55 2021
+++ src/sys/dev/ic/ahcisata_core.c	Wed Jun 23 00:56:41 2021
@@ -1,4 +1,4 @@
-/*	$NetBSD: ahcisata_core.c,v 1.98 2021/04/24 23:36:55 thorpej Exp $	*/
+/*	$NetBSD: ahcisata_core.c,v 1.99 2021/06/23 00:56:41 mrg Exp $	*/
 
 /*
  * Copyright (c) 2006 Manuel Bouyer.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.98 2021/04/24 23:36:55 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.99 2021/06/23 00:56:41 mrg Exp $");
 
 #include <sys/types.h>
 #include <sys/malloc.h>
@@ -144,19 +144,31 @@ static int
 ahci_reset(struct ahci_softc *sc)
 {
 	int i;
+	uint32_t timeout_ms = 1000;	/* default to 1s timeout */
+	prop_dictionary_t dict;
 
 	/* reset controller */
 	AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
-	/* wait up to 1s for reset to complete */
-	for (i = 0; i < 1000; i++) {
+
+	/* some systems (rockchip rk3399) need extra reset time for ahcisata. */
+	dict = device_properties(sc->sc_atac.atac_dev);
+	if (dict)
+		prop_dictionary_get_uint32(dict, "ahci-reset-ms", &timeout_ms);
+
+	/* wait for reset to complete */
+	for (i = 0; i < timeout_ms; i++) {
 		delay(1000);
 		if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
 			break;
 	}
-	if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
-		aprint_error("%s: reset failed\n", AHCINAME(sc));
+	if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) != 0) {
+		aprint_error_dev(sc->sc_atac.atac_dev, "reset failed\n");
 		return -1;
 	}
+	if (i > 1000) {
+		aprint_normal_dev(sc->sc_atac.atac_dev,
+		    "reset took %d milliseconds\n", i);
+	}
 	/* enable ahci mode */
 	ahci_enable(sc);
 

Reply via email to